IS64LV6416AL
64K x 16 HIGH-SPEED CMOS STATIC RAM
ISSI
JANUARY 2006
®
FEATURES
•High-speed access time: 20 ns•CMOS low power operation: 38 mW (typical) operating 10 µW (typical) standby
•TTL compatible interface levels•Single power supply:2.6V (-5%/+10%)
•Fully static operation: no clock or refreshrequired
•Three state outputs
•Data control for upper and lower bytes•Automotive temperature available
DESCRIPTION
The ISSI IS64LV6416AL is a high-speed, 1,048,576-bit
static RAM organized as 65,536 words by 16 bits. It isfabricated using ISSI's high-performance CMOStechnology. This highly reliable process coupled with inno-vative circuit design techniques, yields access times asfast as 20ns with low power consumption.
When CE is HIGH (deselected), the device assumes astandby mode at which the power dissipation can bereduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enableand Output Enable inputs, CE and OE. The active LOWWrite Enable (WE) controls both writing and reading of thememory. A data byte allows Upper Byte (UB) and LowerByte (LB) access.
The IS64LV6416AL is packaged in the JEDEC standard44-pin TSOP-II, 44-pin LQFP, and 48-pin mini BGA (6mmx 8mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A15DECODER64K x 16MEMORY ARRAYVDDGNDI/O0-I/O7Lower ByteI/O8-I/O15Upper ByteI/ODATACIRCUITCOLUMN I/OCEOEWEUBLBCONTROLCIRCUITCopyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liabilityarising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on anypublished information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev. A01/11/06
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IS64LV6416AL
PIN CONFIGURATIONS
48-Pin mini BGA(6mm x 8mm) (B)
1 2 3 4 5 6A15A14A13A12A11CEI/O0I/O1I/O2I/O3VDDGNDI/O4I/O5I/O6I/O7WEA10A9A8A7NC12345678910111213141516171819202122ISSI
44-Pin TSOP-II (T)
®
ABCDEFGHLBI/O8I/O9GNDVDDI/O14I/O15NCOEUBI/O10I/O11I/O12I/O13NCA8A0A3A5NCNCA14A12A9A1A4A6A7NCA15A13A10A2CEI/O1I/O3I/O4I/O5WEA11NCI/O0I/O2VDDGNDI/O6I/O7NC44434241403938373635343332313029282726252423A0A1A2OEUBLBI/O15I/O14I/O13I/O12GNDVDDI/O11I/O10I/O9I/O8NCA3A4A5A6NC44-Pin LQFP (LQ)
PIN DESCRIPTIONS
A0-A15I/O0-I/O15CEOEWELBUBNCVDDGND
Address InputsData Inputs/OutputsChip Enable InputOutput Enable InputWrite Enable Input
Lower-byte Control (I/O0-I/O7)Upper-byte Control (I/O8-I/O15)No ConnectionPowerGround
CEI/O0I/O1I/O2I/O3VDDGNDI/O4I/O5I/O6I/O744434241403938373635345331322313304295TOP VIEW286277268259241023111213141516171819202122WEA0A1A2A3NCNCA4A5A6A7A15A14A13A12A11A10A9A8OEUBLBI/O15I/O14I/O13I/O12GNDVDDI/O11I/O10I/O9I/O8NC2Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev. A01/11/06
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IS64LV6416AL
TRUTH TABLE
Mode
Not SelectedOutput DisabledRead
WEXHXHHHLLL
CEHLLLLLLLL
OEXHXLLLXXX
LBXXHLHLLHL
UBXXHHLLHLL
I/O PIN
I/O0-I/O7I/O8-I/O15High-ZHigh-ZHigh-ZDOUTHigh-ZDOUTDINHigh-ZDIN
High-ZHigh-ZHigh-ZHigh-ZDOUTDOUTHigh-ZDINDIN
ISSI
VDD CurrentISB1, ISB2
ICC
ICC
®
WriteICC
ABSOLUTE MAXIMUM RATINGS(1)
SymbolVTERMTSTGPTVDD
Parameter
Terminal Voltage with Respect to GNDStorage TemperaturePower DissipationVDD Related to GND
Value
–0.5 to VDD+0.5–65 to +150
1.5-0.2 to +3.9
UnitV°CWV
Note:
1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is astress rating only and functional operation of the device at these or any other conditions above those indicated in the operationalsections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affectreliability.
OPERATING RANGE (VDD)
OptionA2A3
Ambient Temperature–40°C to +105°C–40°C to +125°C
VDD (20ns)2.6V -5%/+10%2.6V -5%/+10%
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev. A01/11/06
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IS64LV6416AL
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
SymbolVOHVOLVIHVILILIILO
Parameter
Output HIGH VoltageOutput LOW VoltageInput HIGH VoltageInput LOW Voltage(1)Input LeakageOutput Leakage
GND ≤ VIN ≤ VDD
GND ≤ VOUT ≤ VDD, Outputs DisabledTest Conditions
VDD = Min., IOH = –1.0 mAVDD = Min., IOL = 1.0 mA
Min.2.2—1.7–0.3–1–1
ISSI
Max.—0.4VDD + 0.30.711
VVVVµAµA
®
Unit
Notes:
1.VIL (min.) = –2.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
SymbolParameterICCVDD Dynamic OperatingSupply CurrentOperating SupplyCurrentTTL Standby Current(TTL Inputs)CMOS StandbyCurrent (CMOS Inputs)Test ConditionsVDD = Max.,IOUT = 0 mA, f = fMAXVDD = Max.,Iout = 0mA, f = 0VDD = Max.,VIN = VIH or VILCE ≥ VIH, f = 0VDD = Max.,CE ≥ VDD – 0.2V,VIN ≥ VDD – 0.2V, orVIN ≤ 0.2V, f = 0 -20 nsOptionsMin.Max.A2A3typ(2)A2A3A2A3A2A3typ(2)——————————3035155103430404UnitmAICC1ISB1mAmAISB2uANote:
1.At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.2. Typical values are measured at VDD=2.5V, TA=25oC. Not 100% tested.
CAPACITANCE(1)
SymbolCINCOUT
ParameterInput CapacitanceInput/Output Capacitance
ConditionsVIN = 0VVOUT = 0V
Max.68
UnitpFpF
Note:
1.Tested initially and after any design or process changes that may affect these parameters.
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IS64LV6416AL
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall TimesInput and Output Timingand Reference Level (VRef)Output Load
Unit0V to 2.5V1.5ns1.25VSee Figures 1a and 1b
ISSI
®
AC TEST LOADS
319 ΩZo=50ΩOUTPUT50ΩVRef30 pFIncludingjig and scope2.5VOUTPUT5 pFIncludingjig andscopeFigure 1b.
353 ΩFigure 1a.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev. A01/11/06
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IS64LV6416AL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
ParameterRead Cycle TimeAddress Access TimeOutput Hold TimeCE Access TimeOE Access TimeOE to High-Z OutputOE to Low-Z OutputCE to High-Z OutputCE to Low-Z OutputLB, UB Access TimeLB, UB to High-Z OutputLB, UB to Low-Z Output
-20 nsMin.Max.20—3——0003—00
—20—2088—8—88—
Unitnsnsnsnsnsnsnsnsnsnsnsns
ISSI
®
tRCtAAtOHAtACEtDOEtHZOE(2)tLZOE(2)tHZCE(2tLZCE(2)tBAtHZBtLZB
Notes:
1.Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to2.50V and output loading specified in Figure 1a.
2.Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.3.Not 100% tested.
6Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev. A01/11/06
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IS64LV6416AL
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS = OE = VIL, UB or LB = VIL)
tRCISSI
®
ADDRESStAAtOHAtOHADATA VALIDDOUTPREVIOUS DATA VALIDREAD CYCLE NO. 2(1,3)
tRCADDRESStAAtOHAOEtDOEtHZOECEtLZCEtLZOEtACEtHZCELB, UBtBAtHZB DATA VALIDDOUTHIGH-ZtLZBNotes:
1.WE is HIGH for a Read Cycle.
2.The device is continuously selected. OE, CE, UB, or LB = VIL.3.Address is valid prior to or coincident with CE LOW transition.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev. A01/11/06
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IS64LV6416AL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol
ParameterWrite Cycle TimeCE to Write EndAddress Setup Timeto Write End
Address Hold from Write EndAddress Setup TimeLB, UB Valid to End of WriteWE Pulse Width (OE = HIGH)WE Pulse Width (OE = LOW)Data Setup to Write EndData Hold from Write EndWE LOW to High-Z OutputWE HIGH to Low-Z Output
-20 ns
Min.Max.
2012120012121790—3
——————————9—
Unitnsnsnsnsnsnsnsnsnsnsnsns
ISSI
®
tWCtSCEtAWtHAtSAtPWBtPWE1tPWE2tSDtHDtHZWE(3)tLZWE(3)
Notes:
1.Test conditions for IS64LV6416AL assume signal transition times of 1.5ns or less, timing reference levels of1.25V, input pulse levels of 0 to 2.5V and output loading specified in Figure 1a.
2.Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100%tested.
3.The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must bein valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup andHold timing are referenced to the rising or falling edge of the signal that terminates the write.
8Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev. A01/11/06
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IS64LV6416AL
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
ISSI
t WC®
ADDRESSVALID ADDRESSt SACEt SCEt AWt PWE1t PWE2t PBWt HAWEUB, LBt HZWEDOUTDATA UNDEFINEDHIGH-Zt LZWEt SDDINt HDDATAIN VALIDUB_CEWR1.epsIntegrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev. A01/11/06
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IS64LV6416AL
WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle)t WCADDRESSVALID ADDRESSISSI
®
t HAOECELOWt AWt PWE1WEt SAUB, LBt PBWt HZWEt LZWEHIGH-ZDOUTDATA UNDEFINEDt SDDINt HDDATAIN VALIDUB_CEWR2.epsWRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t WCADDRESSOECEVALID ADDRESSLOWt HALOWt AWt PWE2WEt SAUB, LBt PBWt HZWEt LZWEHIGH-ZDOUTDATA UNDEFINEDt SDDINt HDDATAIN VALIDUB_CEWR3.eps10Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev. A01/11/06
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IS64LV6416AL
WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3)t WCADDRESSADDRESS 1ISSI
t WCADDRESS 2®
OEt SACELOWWEt HAt SAt PBWt PBWWORD 2t HAUB, LBWORD 1t HZWEDOUTDATA UNDEFINEDHIGH-Zt LZWEt HDDATAINVALIDt SDDINt SDDATAINVALIDt HDUB_CEWR4.epsNotes:
1.The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must bein valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing isreferenced to the rising or falling edge of the signal that terminates the Write.
2.Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3.WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev. A01/11/06
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IS64LV6416AL
ISSI
Test ConditionVDD = 1.2V, CE ≥ VDD – 0.2VSee Data Retention WaveformSee Data Retention WaveformO®
DATA RETENTION SWITCHING CHARACTERISTICS
SymbolParameterVDD for Data RetentionData Retention CurrentData Retention Setup TimeRecovery TimeOperationsA2A3Min.1.2——0Typ.(1)—44——Max.3.63040——UnitVµAnsnsVDRIDRSee Data Retention WaveformtSDRtRDRNote:tRC1. Typical values are measured at VDD = 2.5V, TA = 25C. Not 100% tested.DATA RETENTION WAVEFORM (CE Controlled)
tSDRVDD1.65VData Retention ModetRDR1.4VVDRCE ≥ VDD - 0.2VCEGND12Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev. A01/11/06
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IS64LV6416AL
ORDERING INFORMATION
Temperature Range (A2): –40°C to +105°C
Speed (ns)
202020
Order Part No.IS64LV6416AL-20TA2IS64LV6416AL-20BA2IS64LV6416AL-20LQA2
Package
ISSI
®
Plastic TSOP
mini BGA(6mm x 8mm)LQFP
Temperature Range (A3): –40°C to +125°C
Speed (ns)
202020
Order Part No.IS64LV6416AL-20TA3IS64LV6416AL-20BA3IS64LV6416AL-20LQA3
Package
Plastic TSOP
mini BGA(6mm x 8mm)LQFP
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev. A01/11/06
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PACKAGING INFORMATION
LQFP (Low Profile Quad Flat Pack)Package Code: LQ (44-pin)DD1ISSI
®
EE1θbeSEATINGPLANEL1LA2AA1Notes:1.All dimensioning and tolerancingconforms to ANSI Y14.5M-1982.2.Dimensions D1 and E1 do not includemold protrusions. Allowable protrusion is0.25 mm per side. D1 and E1 includemold mismatch.3.Controlling dimension: millimeters.Low Profile Quad Flat Pack (LQ)Ref. Std.MS-026No. Leads 44MillimetersInchesSymbolMinMaxMinMaxA—1.60—0.063A10.050.150.0020.006A21.351.450.0530.057b0.300.450.0120.018C0.090.200.0040.008D12.00 BSC0.472 BSCD110.00 BSC0.394 BSCE12.00 BSC0.472 BSCE110.00 BSC0.394 BSCe0.80 BSC0.031 BSCL0.450.750.0180.030L11.00 REF.0.039 REF.θ0o7o0o7oCopyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised toobtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev.B05/30/03
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PACKAGING INFORMATION
Mini Ball Grid Array
Package Code: B (48-pin)
Top View1 2 3 4 5 6ISSI
Bottom Viewφ b (48x)®
6 5 4 3 2 1ABCDDEFGHD1eABCDEFGHeEE1A2SEATING PLANEA1ANotes:1. Controlling dimensions are in millimeters.mBGA - 6mm x 8mmMILLIMETERSSym.N0.LeadsAA1A2DD1EE1eb— 0.240.607.905.90mBGA - 8mm x 10mmINCHESMin.Typ.Max.Sym.N0.LeadsMILLIMETERMin.Typ.Max. 48— 0.240.609.907.90—————1.200.30—10.108.10—INCHESMin.Typ.Max.Min.Typ.Max.48—————1.200.30—8.106.10—0.0090.0240.3110.232 — ————0.0470.012—0.3190.240AA1A2DD1EE1eb — ————0.0470.012—0.3980.3190.0090.0240.3900.3115.25 BSC3.75 BSC0.75 BSC0.300.350.400.207 BSC0.148 BSC0.030 BSC0.0120.0140.0165.25 BSC3.75 BSC0.75 BSC0.300.350.400.207 BSC0.148 BSC0.030 BSC0.0120.0140.016Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any timewithout notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised toobtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev.D01/15/03
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PACKAGING INFORMATION
Plastic TSOPPackage Code: T (Type II)ISSI
Notes:1.Controlling dimension: millimieters,unless otherwise specified.2.BSC = Basic lead spacingbetween centers.3.Dimensions D and E1 do notinclude mold flash protrusions andshould be measured from thebottom of the package.4.Formed leads shall be planar withrespect to one another within0.004 inches at the seating plane.®
NN/2+1E1E1DN/2ZDASEATING PLANE.ebA1LαCSymbolRef. Std.No. Leads (N)324450A—1.20—0.047—1.20—0.047—1.20—0.047A10.050.150.0020.0060.050.150.0020.0060.050.150.0020.006b0.300.520.0120.0200.300.450.0120.0180.300.450.0120.018C0.120.210.0050.0080.120.210.0050.0080.120.210.0050.008D20.8221.080.8200.83018.3118.520.7210.72920.8221.080.8200.830E110.0310.290.3910.40010.0310.290.3950.40510.0310.290.3950.405E11.5611.960.4510.46611.5611.960.4550.47111.5611.960.4550.471e1.27 BSC 0.050 BSC 0.80 BSC0.032 BSC0.80 BSC 0.031 BSCL0.400.600.0160.0240.410.600.0160.0240.400.600.0160.024ZD 0.95 REF 0.037 REF 0.81 REF 0.032 REF 0.88 REF 0.035 REFα0°5°0°5°0°5°0°5°0°5°0°5°MillimetersMinMaxInchesMinMaxPlastic TSOP (T - Type II)MillimetersInchesMinMaxMinMaxMillimetersMinMaxInchesMinMaxCopyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised toobtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.F06/18/03
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