专利名称：METHODS FOR PACKAGING INTEGRATED
CIRCUITS
发明人：Loon Kwang Tan,Yuanlin Xie,Ping Chet Tan申请号：US14175651申请日：20140207
公开号：US20150228506A1公开日：20150813
专利附图：
摘要：Techniques for packaging an integrated circuit include attaching a die to aconductive layer before forming dielectric layers on an opposing surface of the
conductive layer. The conductive layer may first be formed on a carrier substrate before
the die is disposed on the conductive layer. The die may be electrically coupled to theconductive layer via wires or solder bumps. The carrier substrate is removed before thedielectric layers are formed. The dielectric layers may collectively form a corelesspackage substrate for the integrated circuit package.
申请人：Altera Corporation
地址：San Jose CA US
国籍：US
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