TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSSLAS266C – OCTOBER 2000 – REVISED MAY 2003D14-Bit ResolutionDMaximum Throughput 200 KSPSDAnalog Input Range 0-V to ReferenceDDDDDTLC3548DW OR PW PACKAGE(TOP VIEW)DDDDDDDD VoltageMultiple Analog Inputs:– 8 Channels for TLC3548– 4 Channels for TLC3544Pseudodifferential Analog InputsSPI/DSP-Compatible Serial Interfaces WithSCLK up to 25 MHzSingle 5-V Analog Supply; 3-/5-V DigitalSupplyLow Power:– 4 mA (Internal Reference: 1.8 mA) forNormal Operation– 20 µA in Autopower-DownBuilt-In 4-V Reference, Conversion Clockand 8x FIFOHardware-Controlled and ProgrammableSampling PeriodProgrammable Autochannel Sweep andRepeatHardware Default ConfigurationINL: ±1 LSB MaxDNL: ±1 LSB MaxSINAD: 80.8 dBTHD: –95 dBSCLKFSSDIEOC/INTSDODGNDDVDDCSA0A1A2A31234 56789101112242322212019181716151413CSTARTAVDDAGNDBGAPREFMREFPAGNDAVDDA7A6A5A4TLC3544DW OR PW PACKAGE(TOP VIEW)SCLKFSSDIEOC/INTSDODGNDDVDDCSA0A11234 567891020191817161514131211CSTARTAVDDAGNDBGAPREFMREFPAGNDAVDDA3A2descriptionThe TLC3544 and TLC3548 are a family of 14-bit resolution high-performance, low-power, CMOSanalog-to-digital converters (ADC). All devices operate from a single 5-V analog power supply and 3-V to 5-Vdigital supply. The serial interface consists of four digital inputs [chip select (CS), frame sync (FS), serialinput-output clock (SCLK), serial data input (SDI)], and a 3-state serial data output (SDO). CS (works as SS,slave select), SDI, SDO, and SCLK form an SPI interface. FS, SDI, SDO, and SCLK form a DSP interface. Theframe sync signal (FS) indicates the start of a serial data frame being transferred. When multiple convertersconnect to one serial port of a DSP, CS works as the chip select to allow the host DSP to access the individualconverter. CS can be tied to ground if only one converter is used. FS must be tied to DVDD if it is not used (suchas in an SPI interface). When SDI is tied to DVDD, the device is set in hardware default mode after power-on,and no software configuration is required. In the simplest case, only three wires (SDO, SCLK, and CS or FS)are needed to interface with the host.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright 2000 – 2003, Texas Instruments IncorporatedPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•1SLAS266C – OCTOBER 2000 – REVISED MAY 2003TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSdescription (continued)In addition to being a high-speed ADC with versatile control capability, these devices have an on-chip analogmultiplexer (MUX) that can select any analog input or one of three self-test voltages. The sample-and-holdfunction is automatically started after the fourth SCLK (normal sampling) or can be controlled by CSTART toextend the sampling period (extended sampling). The normal sampling period can also be programmed as shortsampling (12 SCLKs) or long sampling (44 SCLKs) to accommodate the faster SCLK operation popular amonghigh-performance signal processors. The TLC3544 and TLC3548 are designed to operate with low powerconsumption. The power saving feature is further enhanced with software power-down/ autopower-downmodes and programmable conversion speeds. The conversion clock (internal OSC) is built in. The convertercan also use an external SCLK as the conversion clock for maximum flexibility. The TLC3544 and TLC3548have a 4-V internal reference. The converters are specified with unipolar input range of 0-V to 5-V when a 5-Vexternal reference is used.AVAILABLE OPTIONSPACKAGED DEVICESTA0°C to 70°C–40°C to 85°C20-TSSOP(PW)TLC3544CPWTLC3544IPW20-SOIC(DW)TLC3544CDWTLC3544IDW24-SOIC(DW)TLC3548CDWTLC3548IDW24-TSSOP(PW)TLC3548CPWTLC3548IPWfunctional block diagramDVDDREFPBGAPREFM4-VReferenceAVDDX8A0A1A2A3A4A5A6A7X4A0A1A2A3XXXXAnalogMUXOSCSARADCFIFOX8SDOCommandDecodeSDICMR (4 MSBs)ConversionClockCFRSCLKCSFS4-BitCounterCSTARTControlLogicEOC/INTDGNDAGND2POST OFFICE BOX 655303 DALLAS, TEXAS 75265•TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSSLAS266C – OCTOBER 2000 – REVISED MAY 2003equivalent input circuitVDDMUX1.1 kΩMaxAinRonC(sample) = 30 pF MaxVDDDigital InputREFMDiode Turn on Voltage: 35 VEquivalent Analog Input CircuitEquivalent Digital Input CircuitTerminal FunctionsTERMINALNAMEA0A1A2A3A0A1A2A3A4A5A6A7NO.TLC35449101112TLC354891011121314151618, 2217, 23218IAnalog signal inputs. Analog input signals applied to these terminals are internally multiplexed. Thedriving source impedance should be less than or equal to 1 kΩ for normal sampling. For largersource impedance, use the external hardware conversion start signal CSTART (the low time ofCSTART controls the sampling period) or reduce the frequency of SCLK to increase the samplingtime.I/ODESCRIPTIONAGNDAVDDBGAPCS14, 1813, 19178IIIIAnalog ground return for the internal circuitry. Unless otherwise noted, all analog voltagemeasurements are with respect to AGND.Analog supply voltageInternal bandgap compensation pin. Install compensation capacitors between BGAP and AGND.0.1 µF for external reference; 10 µF in parallel with 0.1 µF for internal reference.Chip select. When CS is high, SDO is in high-impedance state, SDI is ignored, and SCLK isdisabled to clock data but works as conversion clock source if programmed. The falling edge of CSinput resets the internal 4-bit counter, enables SDI and SCLK, and removes SDO fromhigh-impedance state.If FS is high at CS falling edge, CS falling edge initiates the operation cycle. CS works as slaveselect (SS) to provide an SPI interface.If FS is low at CS falling edge, FS rising edge initiates the operation cycle. CS can be used as chipselect to allow the host to access the individual converter.CSTART2024IDGNDDVDD6767IIExternal sampling trigger signal, which initiates the sampling from a selected analog input channelwhen the device works in extended sampling mode (asynchronous sampling). A high-to-lowtransition starts the sampling of the analog input signal. A low-to-high transition puts the S/H in holdmode and starts the conversion. The low time of the CSTART signal controls the sampling period.CSTART signal must be long enough for proper sampling. CSTART must stay high long enoughafter the low-to-high transition for the conversion to finish maturely. The activation of CSTART isindependent of SCLK and the level of CS and FS. However, the first CSTART cannot be issuedbefore the rising edge of the 11th SCLK. Tie this terminal to DVDD if not used.Digital ground return for the internal circuitryDigital supply voltagePOST OFFICE BOX 655303 DALLAS, TEXAS 75265•3SLAS266C – OCTOBER 2000 – REVISED MAY 2003TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSTerminal Functions (Continued)TERMINALNAMEEOC(INT)NO.TLC35444TLC35484OEnd of conversion (EOC) or interrupt to host processor (INT)EOC: used in conversion mode 00 only. EOC goes from high to low at the end of the sampling andremains low until the conversion is complete and data is ready.INT: Interrupt to the host processor. The falling edge of INT indicates data is ready for output. INTis cleared by the following CS↓, FS↑, or CSTART↓.FS22IFrame sync input from DSP. The rising edge of FS indicates the start of a serial data frame beingtransferred (coming into or being sent out of the device). If FS is low at the falling edge of CS, therising edge of FS initiates the operation cycle, resets the internal 4-bit counter, and enables SDI,SDO, and SCLK. Tie this pin to DVDD if FS is not used to initiate the operation cycle.External low reference input. Connect REFM to AGND.External positive reference input. When an external reference is used, the range of maximum inputvoltage is determined by the difference between the voltage applied to this terminal and to theREFM terminal. Always install decoupling capacitors (10 µF in parallel with 0.1 µF) between REFPand REFM.Serial clock input from the host processor to clock in the input from SDI and clock out the outputvia SDO. It can also be used as the conversion clock source when the external conversion clockis selected (see Table 2). When CS is low, SCLK is enabled. When CS is high, SCLK is disabledfor the data transfer, but can still work as the conversion clock source.Serial data input. The first 4 MSBs, ID[15:12], are decoded as one 4-bit command. All trailing bits,except for the CONFIGURE WRITE command, are filled with zeros. The CONFIGURE WRITEcommand requires additional 12-bit data. The MSB of input data, ID[15], is latched at the first fallingedge of SCLK following FS falling edge, if FS starts the operation, or latched at the falling edge offirst SCLK following CS falling edge when CS initiates the operation.The remaining input data (if any) is shifted in on the rising edge of SCLK and latched on the fallingedge of SCLK. The input via SDI is ignored after the 4-bit counter counts to 16 (clock edges) or alow-to-high transition of CS, whichever happens first. Refer to the timing specification for the timingrequirements. Tie SDI to DVDD if using hardware default mode (refer to device initialization).The 3-state serial output for the A/D conversion result. All data bits are shifted out through SDO.SDO is in the high-impedance state when CS is high. SDO is released after a CS falling edge. Theoutput format is MSB (OD[15]) first.When FS initiates the operation, the MSB of output via SDO, OD[15], is valid before the first fallingedge of SCLK following the falling edge of FS.When CS initiates the operation, the MSB, OD[15], is valid before the first falling edge of SCLKfollowing the CS falling edge.The remaining data bits are shifted out on the rising edge of SCLK and are valid before the fallingedge of SCLK. Refer to the timing specification for the details.In a select/conversion operation, the first 14 bits are the results from the previous conversion (data).In READ FIFO operation, the data is from FIFO. In both cases, the last two bits are don’t care.In a WRITE operation, the output from SDO is ignored.SDO goes into high-impedance state at the sixteenth falling edge of SCLK after the operation cycleis initiated. SDO is in high-impedance state during conversions in modes 01, 10, and 11.I/ODESCRIPTIONREFMREFP16152019IISCLK11ISDI33ISDO55O4POST OFFICE BOX 655303 DALLAS, TEXAS 75265•TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSSLAS266C – OCTOBER 2000 – REVISED MAY 2003absolute maximum ratings over operating free-air temperature (unless otherwise noted)†Supply voltage, GND to AVDD, DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 VAnalog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.2 V to AVDD +0.2 VAnalog input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA MAXReference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVDD + 0.3 VDigital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 VOperating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°COperating free-air industrial temperature range, TA:I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°CC suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°CStorage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°CLead temperature 1,6 mm (1.16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•5SLAS266C – OCTOBER 2000 – REVISED MAY 2003TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSgeneral electrical characteristics over recommended operating free-air temperature range,single-ended input, normal long sampling, 200 KSPS, AVDD = 5 V, external reference (VREFP = 4 V,VREFM = 0V) or internal reference, SCLK frequency = 25 MHz, fixed channel at CONV mode 00,analog input signal source resistance = 25 Ω (unless otherwise noted)PARAMETERDigital InputVIHVILIIHIILDigital outputVOHHighlevel digital outut,High-level digital output,VOH at 30-pF loadLow-level digital output,Lowlevel digital outut,VOL at 30-pF loadOffstate outut currentOff-state output current(high-impedance state)IO = =–0.2 mA02mADVDD = 5 V=5VDVDD = 3 V=3VVO = DVDDVO = DGNDDVDD = 5 VDVDD = 3 VIO = 0.8 mAIO = 50 µAIO = 0.8 mAIO = 50 µACSDVDDCS = DV0.02–14.52.7AVDD current-AICCDVDD current-DICCConversion clock is internal OSC,EXT. reference, AVEXTreferenceAVDD = 5.5 V to 4.5 V,=55Vto45VCS = DGNDSCLK ONSCLK OFFSCLK ONSCLK OFF0–40–0.02552.81.2175201752070852305.55.53.6mA2240µA4.22.40.40.10.40.11µAVVHighlevelcontrolinputvoltageHigh-level control input voltageLow-level control input voltageLowlevel control inut voltageHigh-level input currentLow-level input currentInput capacitanceDVDD = 5 VDVDD = 3 VDVDD = 5 VDVDD = 3 VVI = DVDDVI = DGND0.005–2.50.00520253.82.10.80.62.5VVµAµApFTEST CONDITIONSMINTYP†MAXUNITVOLIOZPower SupplyAVDDDVDDICCSupplyvoltageSupply voltageVVPower sulyPower supplycurrentICC(SW)For all digital inputs DVDD orCS=DVDD,DGND, CS = DV supply lcurrent SftSoftwarepower-downdpowertDGNDAVDD = 5.5 VAutopower-down power supplycurrentFor all digital inputs DVDD orDGND, AVDGNDAVDD = 5.5 V,=55VExternal referenceC suffixI suffixICC(Autodown)CC(Atd)µAOperatingtemperatreOperating temperature†All typical values are at TA = 25°C.°C6POST OFFICE BOX 655303 DALLAS, TEXAS 75265•TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSSLAS266C – OCTOBER 2000 – REVISED MAY 2003general electrical characteristics over recommended operating free-air temperature range,single-ended input, normal long sampling, 200 KSPS, AVDD = 5 V, external reference (VREFP = 4V,VREFM = 0V) or internal reference, SCLK frequency = 25 MHz, fixed channel at CONV mode 00,analog input signal source resistance = 25 Ω (unless otherwise noted) (continued)PARAMETERResolutionAnalog InputVoltage rangeLeakage currentCapacitanceReferenceInternal reference voltageInternal reference temperaturecoefficientInternal reference source currentInternal reference startup timeVREFPVREFMExternal positive reference voltageExternal negative reference voltageNo conversion (AVDD = 5 V,CS = DVDD, SCLK = DGND)Normal long sampling (AVDD = 5 V,CS = DGND, SCLK = 25 MHz,External conversion clock)No conversion (VREFP = AVDD = 5 V,VREFM = AGND, External reference,CS = DVDD)Normal long sampling (AVDD = 5 V,CS = DGND, SCLK = 25 MHz externalconversion clock at VREF = 5 V)DVDD = 2.7 V to 5.5 VInternal OSC, 6.5 MHz minutet(conv)Conversion timeAcquisition timeThroughput rate (see Note 2)DC Accuracy—Normal Long SamplingELEDIntegral linearity errorDifferential linearity errorSee Note 3–1–1±0.5±0.511LSBLSBConversion clock is external source,SCLK = 25 MHz (see Note 1)Normal short samplingNormal long sampling, fixed channel in mode00 or 012002.8951.26.52.785µsµsKSPS301008.312.5AGND3.8541001.82052.54.07Vppm/°CmAmsVVMΩkΩ0Reference0.010.0530VµApFTEST CONDITIONSMIN14TYP†MAXUNITbitsExternal reference input impedance1.5µAExternalreferencecurrentExternal reference current0.40.6mAThroughput RatefInternal oscillation frequencyMHzEOZero offset errorSee Note 4–3±0.63LSBE(g+)Gain errorSee Note 40512LSB†All typical values are at TA = 25°C.NOTES:1.Conversion time t(conv) = (18x4 / SCLK) + 15 ns.2.This is for a fixed channel in conversion mode 00 or 01. When switching the channels, additional multiplexer setting time is requiredto overcome the memory effect of the charge redistribution DAC (refer to Figure 8).3.Linear error is the maximum deviation from the best fit straight line through the A/D transfer characteristics.4.Zero offset error is the difference between 0000000000000 and the converted output for zero input voltage; gain error is thedifference between 11111111111111 and the converted output for full-scale input voltage. The full-scale input voltage is equal to thereference voltage being used.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•7SLAS266C – OCTOBER 2000 – REVISED MAY 2003TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSgeneral electrical characteristics over recommended operating free-air temperature range,single-ended input, normal long sampling, 200 KSPS, AVDD = 5 V, external reference (VREFP = 4V,VREFM = 0V) or internal reference, SCLK frequency = 25 MHz, fixed channel at CONV mode 00,analog input signal source resistance = 25 Ω (unless otherwise noted) (continued)PARAMETERDC Accuracy—Normal Short SamplingELEDIntegral linearity errorDifferential linearity errorSee Note 4See Note 4fi = 20 kHzfi = 100 kHzfi = 20 kHzfi = 100 kHzfi = 20 kHzfi = 100 kHzfi = 20 kHzfi = 100 kHzfi = 20 kHzfi = 100 kHzFixed channel in conversion mode 00, fi = 35 kHzFull power bandwidth, –1 dBFull power bandwidth, –3 dBfi = 20 kHzfi = 100 kHzfi = 20 kHzfi = 100 kHzfi = 20 kHzfi = 100 kHzfi = 20 kHzfi = 100 kHzfi = 20 kHzfi = 100 kHzFixed channel in conversion mode 00, fi = 35 kHzFull power bandwidth, –1 dBFull power bandwidth, –3 dB9012.879–3078.6See Note 3TEST CONDITIONSMINTYP†±0.8±0.6±0.6580.877.6–95–88978913.112.6817810022.578.977.6–95–88797812.812.6978910022.5–90312MAXUNITLSBLSBLSBLSBEOZero offset errorE(g+)Gain errorAC Accuracy—Normal Long SamplingSINADTHDSFDRENOBSNRSignaltonoiseratio+distortionSignal-to-noise ratio + distortionTotalharmonicdistortionTotal harmonic distortionSpuriousfreedynamicrangeSpurious free dynamic rangeEffectivenumberofbitsEffective number of bitsSignaltonoiseratioSignal-to-noise ratioChannel-to-channel isolation (seeNotes 2 and 5)AnaloginputbandwidthAnalog input bandwidthAC Accuracy—Normal Short SamplingSINADTHDSNRENOBSFDRSignaltonoiseratio+distortionSignal-to-noise ratio + distortionTotalharmonicdistortionTotal harmonic distortionSignaltonoiseratioSignal-to-noise ratioEffectivenumberofbitsEffective number of bitsSpuriousfreedynamicrangeSpurious free dynamic rangeChannel-to-channel isolation (seeNotes 2 and 5)AnaloginputbandwidthAnalog input bandwidthdBdBdBBitsdBdBMHzdBdBdBBitsdBdBMHz†All typical values are at TA = 25°C.NOTES:2.This is for a fixed channel in conversion mode 00 or 01. When switching the channels, additional multiplexer setting time is requiredto overcome the memory effect of the charge redistribution DAC (refer to Figure 8).3.Linear error is the maximum deviation from the best fit straight line through the A/D transfer characteristics.4.Zero offset error is the difference between 0000000000000 and the converted output for zero input voltage; gain error is thedifference between 11111111111111 and the converted output for full-scale input voltage. The full-scale input voltage is equal to thereference voltage being used.5.It is measured by applying a full-scale of 35 kHz signal to other channels and determining how much the signal is attenuated in thechannel of interest. The converter samples this examined channel continuously. The channel-to-channel isolation is degraded if theconverter samples different channels alternately (refer to Figure 8).8POST OFFICE BOX 655303 DALLAS, TEXAS 75265•TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSSLAS266C – OCTOBER 2000 – REVISED MAY 2003timing requirements over recommended operating free-air temperature range, AVDD = 5 V, DVDD= 5 V, VREFP = 5 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted)SCLK, SDI, SDO, EOC and INTPARAMETERStc(1)(1)tw(1)tr(1)tf(1)tsu(1)th(1)td(1)th(2)td(2)td(3)CycletimeofSCLKat25pFloadCycle time of SCLK at 25-pF loadPulse width, SCLK high time at 25-pF loadRisetimeforINTEOCat10pFloadRise time for INT, EOC at 10-pF loadFalltimeforINTEOCat10pFloadFall time for INT, EOC at 10-pF loadDVDD = 5 VDVDD = 2.7 VDVDD = 5 VDVDD = 2.7 V600000t(conv)DVDD = 2.7 VDVDD = 5 VMIN10040†40%60%610610––1023‡–6t(conv) + 6TYPMAXUNITnstc(1)nsnsnsnsnsnsnsµsSetup time, new SDI valid (reaches 90% final level) before falling edge of SCLK, at 25-pFloadHold time, old SDI hold (reaches 10% of old data level) after falling edge of SCLK, at25-pF loadDelay time, new SDO valid (reaches 90% of final level) after SCLK risingedge, at 10-pF loadDVDD= 5 VDVDD = 2.7 VHold time, old SDO hold (reaches 10% of old data level) after SCLK rising edge, at 10-pFloadDelay time, delay from sixteenth SCLK falling edge to EOC falling edge, normal sampling,at 10-pF loadDelay time, delay from the sixteenth falling edge of SCLK to INT falling edge, at 10-pFload [see the (‡) double dagger note and Note 6]†The minimum pulse width of SCLK high is 12.5 ns. The minimum pulse width of SCLK low is 12.5 ns.‡Specified by designNOTE 6:For normal short sampling, td(3) is the delay from 16th falling edge of SCLK to INT falling edge.For normal long sampling, td(3) is the delay from 48th falling edge of SCLK to the falling edge of INT.Conversion time, t(conv) is equal to 18 × OSC + 15 ns when using internal OSC as conversion clock, or 72 × tc(1) + 15 ns when externalSCLK is conversion clock source.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•9SLAS266C – OCTOBER 2000 – REVISED MAY 2003TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSCS90%50%10%VIHVILtc(1)tw(1)SCLKtsu(1)SDIDon’t Care116th(1)ID15ID1td(1)th(2)ID0Don’t CareSDOHi-ZOD15OD1OD0td(2)See Note Atr(1)Hi-ZEOCORINTtf(1)td(3)See Note Btf(1)tr(1)NOTES:A.For normal long sampling, td(2) is the delay time of EOC low after the falling edge of 48th SCLK.B.For normal long sampling, td(3) is the delay time of INT low after the falling edge of 48th SCLK. – – – – The dotted line means signal may or may not exist, depending on application. It must be ignored. Normal sampling mode, CS initiates the conversion, FS must be tied to high. When CS is high, SDO is in Hi-Z; all inputs (FS, SCLK,SDI) are inactive and are ignored.Figure 1. Critical Timing for SCLK, SDI, SDO, EOC and INT10POST OFFICE BOX 655303 DALLAS, TEXAS 75265•TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSSLAS266C – OCTOBER 2000 – REVISED MAY 2003timing requirements over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, VREFP = 5 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued)CS triggerPARAMETERStsu(2)td(4)tw(2)td(5)td(6)td(7)Setup time, CS falling edge before SCLK rising edge, at 25-pF loadDelay time, delay time from 16th SCLK falling edge to CS rising edge, at 25-pF load ‡Pulse width, CS high time at 25-pF loadDelay time, delay from CS falling edge to MSB of SDO valid (reaches 90%final level), at 10-pF loadDelay time, delay from CS rising edge to SDO 3-state, at 10-pF loadDelaytimedelayfromCSfallingedgetoINTrisingedgeat10pFloadDelay time, delay from CS falling edge to INT rising edge, at 10-pF loadDVDD = 5 VDVDD = 2.7 VDVDD = 5 VDVDD = 2.7 VMIN1251000001230†6616†TYPMAXUNITnsnstc(1)nsnsns†Specified by design‡For normal short sampling, td(4) is the delay time from 16th SCLK falling edge to CS rising edge.For normal long sampling, td(4) is the delay time from 48th SCLK falling edge to CS rising edge.VIHVILtsu(2)SCLK116td(4)tw(2)CSSDIDon’t CareHi-Ztd(5)ID15ID1ID0Don’t CareHi-ZDon’t Caretd(6)Hi-ZSDOOD15OD1OD0OD15OD7EOCORINTtd(7)NOTE A: – – – – The dotted line means signal may or may not exist, depending on application. It must be ignored.Normal sampling mode, CS initiates the conversion, FS must be tied to high. When CS is high, SDO is in Hi-Z, all inputs (FS, SCLK,SDI) are inactive and are ignored. Parts with date code earlier than 13XXXXX have these discrepancies:(Date code is a 7 digit code next to the TI where the first digit indicates the year and the second digit is the month of production. 13,in this case, is 2001 and the month of March.) FS is not ignored even if the device is in microcontroller mode (CS triggered).FS must be tied to DVDD.Figure 2. Critical Timing for CS TriggerPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•11SLAS266C – OCTOBER 2000 – REVISED MAY 2003TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTStiming requirements over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, VREFP = 5 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued)FS triggerPARAMETERStd(8)tsu(3)tw(3)td(9)td(10)Delay time, delay from CS falling edge to FS rising edge, at 25-pF loadSetup time, FS rising edge before SCLK falling edge, at 25-pF loadPulse width, FS high at 25-pF loadDelay time, delay from FS rising edge to MSB of SDO valid(reaches 90% final level) at 10-pF loadDVDD = 5 VDVDD = 2.7 VRequiredsampling time +conversion time06†16†MIN0.50.25×tc(1)0.75×tc(1)tc(1)0.5×tc(1)+51.25×tc(1)26†30†TYPMAXUNITtc(1)nsnsnsDelay time, delay from FS rising edge to next FS rising edge at 25-pF loadDelay time, delay from FS rising edge to INT rising edge at10-pF loadDVDD = 5 VDVDD = 2.7 Vµstd(11)ns†Specified by designtd(10)td(8)FStsu(3)SCLK116tw(3)CSVIHVILSDIDon’t Caretd(9)ID15ID1ID0Don’t CareID15Don’t CareSDOEOCORINTHi-ZVOHVOHOD15OD1OD0Hi-ZOD15Don’t Caretd(11)NOTE A: – – – – The dotted line means signal may or may not exist, depending on application. It must be ignored.Normal sampling mode, FS initiates the conversion, CS can be tied to low. When CS is high, SDO is in Hi-Z, all inputs (FS, SCLK, SDI)are inactive and are ignored.Parts with date code earlier than 13XXXXX have these discrepancies:(Date code is a 7 digit code next to the TI where the first digit indicates the year and the second digit is the month of production. 13,in this case, is 2001 and the month of March.) SDO MSB (OD[15]) comes out from the falling edge of CS instead of FS rising edge in DSP mode (FS triggered).Figure 3. Critical Timing for FS Trigger12POST OFFICE BOX 655303 DALLAS, TEXAS 75265•TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSSLAS266C – OCTOBER 2000 – REVISED MAY 2003timing requirements over recommended operating free-air temperature range, AVDD = 5 V, DVDD = 5 V, VREFP = 5 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued)CSTART triggerPARAMETERStd(12)tw(4)td(13)td(14)td(15)Delay time, delay from CSTART rising edge to EOC fallingedge, at 10-pF loadPulse width CSTART low time: tW(L)(CSTART), at 25-pF loadDelay time, delay from CSTART rising edge to CSTART fallingedge, at 25-pF loadDelay time, delay from CSTART rising edge to INT falling edge,at 10-pF loadDelay time, delay from CSTART falling edge to INT rising edge,at 10-pF loadMIN0t(sample – ref)+0.4t(conv) +15t(conv) +150TYP15Note 7Notes 7 and 8Notes 7 and 8t(conv)+216MAX21UNITnsµsnsnsµsNOTES:7.The pulse width of CSTART must be not less than the required sampling time. The delay from CSTART rising edge to followingCSTART falling edge must not be less than the required conversion time. The delay from CSTART rising edge to the INT falling edgeis equal to the conversion time.8.The maximum rate of SCLK is 25 MHz for normal long sampling and 10 MHz for normal short sampling.tw(4)CSTARTtd(12)EOCtd(15)ORtd(14)INTtd(13)t(conv)Extended SamplingFigure 4. Critical Timing for Extended Sampling (CSTART Trigger)detailed descriptionconverterThe converters are a successive-approximation ADC utilizing a charge redistribution DAC. Figure5 shows asimplified block diagram of the ADC. The sampling capacitor acquires the signal on Ain during the samplingperiod. When the conversion process starts, the control logic directs the charge redistribution DAC to add andsubtract fixed amounts of charge from the sampling capacitor to bring the comparator into a balanced condition.When balanced, the conversion is complete and the ADC output code is generated.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•13SLAS266C – OCTOBER 2000 – REVISED MAY 2003TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSdetailed description (continued)ChargeRedistributionDACAin_+ControlLogicADC CodeREFMFigure 5. Simplified Block Diagram of the Successive-Approximation Systemanalog input range and internal test voltagesTLC3548 has eight analog inputs (TLC3544 has four) and three test voltages. The inputs are selected by theanalog multiplexer according to the command entered (see Table 1). The input multiplexer is a break-before-make type to reduce input-to-input noise injection resulting from channel switching.The TLC3544 and TLC3548 are specified for a unipolar input range of 0-V to 4-V when the internal referenceis selected, and 0-V to 5-V when an external 5-V reference is used.analog input modeTwo input signal modes can be selected: single-ended input and pseudodifferential input.ChargeRedistributionDACS1Ain(+)Ain(–)_+ControlLogicADC CodeREFMWhen sampling, S1 is closed and S2 connects to Ain(–).During conversion, S1 is open and S2 connects to REFM.Figure 6. Simplified Pseudodifferential Input CircuitPseudodifferential input refers to the negative input, Ain(–); its voltage is limited in magnitude to ±0.2 V. The inputfrequency limit of Ain(–) is the same as the positive input Ain(+). This mode is normally used for ground noiserejection or dc bias offset.When pseudodifferential mode is selected, only two analog input channel pairs are available for the TLC3544and four channel pairs for the TLC3548, because half the inputs are used as the negative input (see Figure 7).14POST OFFICE BOX 655303 DALLAS, TEXAS 75265•TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSSLAS266C – OCTOBER 2000 – REVISED MAY 2003analog input mode (continued)Single EndedX8†X4‡A0A0A1A1A2A2A3A3XA4XA5XA6XA7X8†A0(+) Pair AA1(–) A2(+) Pair BA3(–) A4(+) Pair CA5(–) A6(+) Pair DA7(–) PseudodifferentialX4‡ A0(+) Pair AA1(–) A2(+) Pair BA3(–) AnalogMUXSARADCAnalogMUXSARADC†TLC3548‡TLC3544Figure 7. Pin Assignment of Single-Ended Input vs Pseudodifferential Inputreference voltageThere is a built-in 4-V reference. If the internal reference is used, REFP is internally set to 4-V and REFM is setto 0-V. The external reference can be applied to the reference-input pins (REFP and REFM) if programmed (seeTable 2). The REFM pin should connect to analog ground. REFP can be 3-V to 5-V. Install decoupling capacitors(10 µF in parallel with 0.1 µF) between REFP and REFM. Install compensation capacitors (10 µF in parallel with0.1 µF for internal reference, 0.1 µF only for external reference) between BGAP and AGND.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•15SLAS266C – OCTOBER 2000 – REVISED MAY 2003TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSdetailed description (continued)ideal conversion characteristics2s ComplementBTC011111111111110111111111111001111111111101Digital Output CodeBinaryUSB111111111111111111111111111011111111111101163831638216381000000000000010000000000000011111111111111100000000000011000000000000001111111111111819381928191100000000000101000000000000110000000000000000000000000100000000000000100000000000000210VREFP = VFS = 4 VVREFM = VZS = 0 V122 µV244 µV488 µVUnipolar Analog Input Voltage1 LSB = 244 µV1.999878 V2.000122 VVFS – 1 LSB = 3.999756 V3.999512 VVMS = (VFS + VZS)/2 = 2 Vdata formatINPUT DATA FORMAT (BINARY)MSBID[15:12]CommandLSBID[11:0]Configuration data field or filled with zeros14-BITUnipolar Straight Binary Output: (USB)Zero-scale code = VZS = 0000h, Vcode = VREFMMid-scale code = VMS = 2000h, Vcode = VREFP/2Full-scale code = VFS = 3FFFh, Vcode = VREFT – 1 LSBUnIpolar Input, Binary 2’s Complement Output: (BTC)Zero-scale code = VZS = 2000 h, Vcode = VREFMMid-scale code = VMS = 0000h, Vcode = (VREFP – VREFM)/2Full-scale code = VFS = 1FFFh, Vcode = VREFP – 1 LSBOUTPUT DATA FORMAT READ CONVERSION/FIFOMSBOD[15:2]Conversion resultLSBOD[1:0]Don’t Care16POST OFFICE BOX 655303 DALLAS, TEXAS 75265•StepTLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSSLAS266C – OCTOBER 2000 – REVISED MAY 2003detailed description (continued)operation descriptionThe converter samples the selected analog input signal, then converts the sample into digital output, accordingto the selected output format. The converter has four digital input pins (SDI, SCLK, CS, and FS) and one digitaloutput pin (SDO) to communicate with the host device. SDI is a serial data input pin, SDO is a serial data outputpin, and SCLK is a serial clock from the host device. This clock is used to clock the serial data transfer. It canalso be used as the conversion clock source (see Table 2). CS and FS are used to start the operation. Theconverter has a CSTART pin for an external hardware sampling and conversion trigger, and an INT/EOC pinfor interrupt purposes.device initializationAfter power on, the status of EOC/INT is initially high, and the input data register is set to all zeros. The devicemust be initialized before starting the conversion. The initialization procedure depends on the working mode.The first conversion result is ignored after power on.Hardware Default Mode: Nonprogrammed Mode, Default. After power on, two consecutive active cyclesinitiated by CS or FS put the device into hardware default mode if SDI is tied to DVDD. Each of these cycles mustlast 16 SCLKs at least. These cycles initialize the converter and load the CFR register with 800h (externalreference, unipolar straight binary output code, normal long sampling, internal OSC, single-ended input,one-shot conversion mode, and EOC/INT pin as INT). No additional software configuration is required.Software Programmed Mode: Programmed. When the converter has to be configured, the host must writeA000h into the converter first after power on, then perform the WRITE CFR operation to configure the device.start of operation cycleEach operation consists of several actions that the converter takes according to the command from the host.The operation cycle includes three periods: command period, sampling period, and conversion period. In thecommand period, the device decodes the command from the host. In the sampling period, the device samplesthe selected analog signal according to the command. In the conversion period, the sample of the analog signalis converted to digital format. The operation cycle starts from the command period, which is followed by oneor several sampling and conversion periods (depending on the setting) and finishes at the end of the lastconversion period.The operation cycle is initiated by the falling edge of CS or the rising edge of FS.CS Initiates The Operation: If FS is high at the falling edge of CS, the falling edge of CS initiates the operation.When CS is high, SDO is in the high-impedance state, the signals on SDI, and SDO are ignored, and SCLK isdisabled to clock the serial data. The falling edge of CS resets the internal 4-bit counter and enables SDO, SDI,and SCLK. The MSB of the input data via SDI, ID[15], is latched at the first falling edge of SCLK following thefalling edge of CS. The MSB of output data from SDO, OD[15], is valid before this SCLK falling edge. This modeworks as an SPI interface when CS is used as the slave select (SS). It also can be used as a normal DSPinterface if CS connects to the frame sync output of the host DSP. FS must be tied high in this mode.FS Initiates The Operation: If FS is low at the falling edge of CS, the rising edge of FS initiates the operation,resets the internal 4-bit counter, and enables SDI, SDO, and SCLK. The ID[15] is latched at the first falling edgeof SCLK following the falling edge of FS. OD[15] is valid before this falling edge of SCLK. This mode is usedto interface the converter with a serial port of the host DSP. The FS of the device is connected to the frame syncof the host DSP. When several devices are connected to one DSP serial port, CS is used as chip select to allowthe host DSP to access each device individually. If only one converter is used, CS can be tied low.After the initiation, the remaining SDI data bits (if any) are shifted in and the remaining bits of SDO (if any) areshifted out at the rising edge of SCLK. The input data are latched at the falling edge of SCLK, and the outputdata are valid before this falling edge of SCLK. After the 4-bit counter reaches 16, the SDO goes to ahigh-impedance state. The output data from SDO is the previous conversion result in one shot conversionmode, or the contents in the top of the FIFO when the FIFO is used (refer to Figure 21).POST OFFICE BOX 655303 DALLAS, TEXAS 75265•17SLAS266C – OCTOBER 2000 – REVISED MAY 2003TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSdetailed description (continued)command periodAfter the rising edge of FS (FS triggers the operation) or the falling edge of CS (CS triggers the operation), SDI,SDO, and SCLK are enabled. The first four SCLK clocks form the command period. The four MSBs of input data,ID[15:12], are shifted in and decoded. These bits represent one of the 4-bit commands from the host, whichdefines the required operation (see Table 1, Command Set). The four MSBs of output, OD[15:12], are alsoshifted out via SDO during this period.The commands are SELECT/CONVERSION, WRITE CFR, FIFO READ, SW POWER DOWN, andHARDWARE DEFAULT mode. The SELECT/CONVERSION command includes SELECT ANALOG INPUTand SELECT TEST commands. All cause a select/conversion operation. They select the analog signal beingconverted, and start the sampling/conversion process after the selection. WRITE CFR causes the configurationoperation, which writes the device configuration information into the CFR register. FIFO READ reads thecontents in the FIFO. SW POWER DOWN puts the device into software power-down mode to save power.Hardware default mode sets the device into the hardware default mode.After the command period, the remaining 12 bits of SDI are written into the CFR register to configure the deviceif the command is WRITE CFR. Otherwise, these bits are ignored. The configuration is retained in theautopower-down and software power-down state. If SCLK stops (while CS remains low) after the first eight bitsare entered, the next eight bits can be entered after SCLK resumes. The data on SDI are ignored after the 4-bitcounter counts to 16 (falling edge of SCLK) or the low-to-high transition of CS, whichever happens first.The remaining 12 bits of output data are shifted out from SDO if the command is SELECT/CONVERSION orFIFO READ. Otherwise, the data on SDO are ignored. In any case, SDO goes into a high-impedance state afterthe 4-bit counter counts to 16 (falling edge of SCLK) or the low-to-high transition of CS, whichever happens first.Table 1. Command Set (CMR)SDI Bit D[15:12]BINARY0000b0001b0010b0011b0100b0101b0110b0111b1000b1001b1010b1011b1100b1101b1110b1111bHEX0h1h2h3h4h5h6h7h8h9hAhBhChDhEhFhTLC3548COMMANDTLC3548 COMMANDSELECT analog input channel 0SELECT analog input channel 1SELECT analog input channel 2SELECT analog input channel 3SELECT analog input channel 4SELECT analog input channel 5SELECT analog input channel 6SELECT analog input channel 7SW POWER DOWNReserved (test)WRITE CFR, the last 12 bits of SDI are written into CFR. This command resets FIFO.SELECT TEST, voltage = (REFP+REFM)/2 (see Notes 9 and 10)SELECT TEST, voltage = REFM (see Note 11)SELECT TEST, voltage = REFP (see Note 12)FIFO READ, FIFO contents is shown on SDO; OD[15:2] = result, OD[1:0] = xxHardware default mode, CFR is loaded with 800hTLC3544COMMANDTLC3544 COMMANDSELECT analog input channel 0SELECT analog input channel 1SELECT analog input channel 2SELECT analog input channel 3SELECT analog input channel 0SELECT analog input channel 1SELECT analog input channel 2SELECT analog input channel 3NOTES:9.REFP is external reference if external reference is selected, or internal reference if internal referenceis programmed.10.The output code = mid-scale code + zero offset error + gain error.11.The output code = zero scale code + zero offset error.12.The output code = full-scale code + gain error.18POST OFFICE BOX 655303 DALLAS, TEXAS 75265•TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSSLAS266C – OCTOBER 2000 – REVISED MAY 2003detailed description (continued)Table 2. Configuration Register (CFR) Bit DefinitionSDI BITD11D10D9D8D7Reference select:0: Internal (4 V)Conversion output code format select:0: USB (unipolar straight binary)Sample period select for normal sampling0: Long sampling (4X) 44 SCLKsConversion clock source select:0: Conversion clock = Internal OSCInput mode select:0: Single-endedPin No.910111213141516D[6:5]Single-endedA0A1A2A3A4A5A6A7DEFINITION1: External1: Binary 2s complementDon’t care in extended sampling.1: Short sampling (1X) 12 SCLKs1: Conversion clock = SCLK/41: Pseudodifferential. Pin configuration shown below.Pin Configuration of TLC3544Pin No.9101112Single-endedA0A1A2A3Pseudodifferential polarityPLUSMINUSPLUSMINUSPair APair BPseudodifferential polarityPLUSMINUSPLUSMINUSPLUSMINUSPLUSMINUSPair APair BPair CPair DPin Configuration of TLC3548Conversion mode select:00: One shot mode01: Repeat mode10: Sweep mode11: Repeat sweep modeSweep auto sequence select (Note: These bits only take effect in conversion mode 10 and 11.)TLC3548Single ended(by ch)00: 0–1–2–3–4–5–6–701: 0–2–4–6–0–2–4–610: 0–0–2–2–4–4–6–611: 0–2–0–2–0–2–0–2Pseudodifferential (by pair)00: N/A01: A–B–C–D–A–B–C–D10: A–A–B–B–C–C–D–D11: A–B–A–B–A–B–A–BSingle ended (by ch)00: 0–1–2–3–0–1–2–301: 0–2–0–2–0–2–0–210: 0–0–1–1–2–2–3–311: 0–0–0–0–2–2–2–2TLC3544Pseudodifferential (by pair)00: N/A01: A–B–A–B–A–B–A–B10: N/A11: A–A–A–A–B–B–B–BD[4:3][]D2D[1:0]EOC/INT pin function select:0: Pin used as INT1: Pin used as EOC ( for mode 00 only)FIFO trigger level (sweep sequence length). Don’t care in one shot mode.00: Full (INT generated after FIFO level 7 filled)01: 3/4 (INT generated after FIFO level 5 filled)10: 1/2 (INT generated after FIFO level 3 filled)11: 1/4 (INT generated after FIFO level 1 filled)sampling periodThe sampling period follows the command period. The selected signal is sampled during this time. The devicehas three different sampling modes: normal short mode, normal long mode, and extended mode.Normal Short Sampling Mode: Sampling time is controlled by SCLK. It takes 12 SCLK periods. At the end ofsampling, the converter automatically starts the conversion period. After configuration, normal sampling, exceptFIFO READ and WRITE CFR commands, starts automatically after the fourth falling edge of SCLK that followsthe falling edge of CS if CS triggers the operation, or follows the rising edge of FS if FS initiates the operation.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•19SLAS266C – OCTOBER 2000 – REVISED MAY 2003TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSsampling period (continued)Normal Long Sampling Mode: This mode is the same as normal short sampling, except that it lasts 44 SCLKperiods.Extended Sampling Mode: The external trigger signal, CSTART, triggers sampling and conversion. SCLK isnot used for sampling. SCLK is also not needed for conversion if the internal conversion clock is selected. Thefalling edge of CSTART begins the sampling of the selected analog input. The sampling continues whileCSTART is low. The rising edge of CSTART ends the sampling and starts the conversion (with about 15 nsinternal delay). The occurrence of CSTART is independent of the SCLK clock, CS, and FS. However, the firstCSTART cannot occur before the rising edge of the 11th SCLK. In other words, the falling edge of the firstCSTART can happen at or after the rising edge of the 11th SCLK, but not before. The device enters the extendedsampling mode at the falling edge of CSTART and exits this mode once CSTART goes to high followed by twoconsecutive falling edges of CS or two consecutive rising edges of FS (such as one read data operation followedby a write CFR). The first CS or FS does not cause conversion. Extended mode is used when a fast SCLK isnot suitable for sampling, or when an extended sampling period is needed to accommodate different input signalsource impedance.conversion periodThe conversion period is the third portion of the operation cycle. It begins after the falling edge of the 16th SCLKfor normal short sampling mode, or after the falling edge of the 48th SCLK for normal long sampling, or on therising edge of CSTART (with 15 ns internal delay) for extended sampling mode.The conversion takes 18 conversion clocks plus 15 ns. The conversion clock source can be an internal oscillator,OSC, or an external clock, SCLK. The conversion clock is equal to the internal OSC if the internal clock is used,or equal to SCLK/4 when the external clock is programmed. To avoid premature termination of the conversion,enough time for the conversion must be allowed between consecutive triggers. EOC goes low at the beginningof the conversion period and goes high at the end of the conversion period. INT goes low at the end of this period.conversion modeFour different conversion modes (mode 00, 01, 10, 11) are available. The operation of each mode is slightlydifferent, depending on how the converter samples and what host interface is used. Do not mix different typesof triggers throughout the repeat or sweep operations.One Shot Mode (Mode 00): Each operation cycle performs one sampling and one conversion for the selectedchannel. The FIFO is not used. When EOC is selected, it is generated while the conversion period is in progress.Otherwise, INT is generated after the conversion is done. The result is output through the SDO pin during thenext select/conversion operation.Repeat Mode (Mode 01): Each operation cycle performs multiple samplings and conversions for a fixedchannel selected according to the 4-bit command. The results are stored in the FIFO. The number of samplesto be taken is equal to the FIFO threshold programmed via D[1:0] in the CFR register. Once the threshold isreached, INT is generated, and the operation ends. If the FIFO is not read after the conversions, the data arereplaced in the next operation. The operation of this mode starts with the WRITE CFR command to setconversion mode 01, then the SELECT/CONVERSION command, followed by a number of samplings andconversions of the fixed channel (triggered by CS, FS, or CSTART) until the FIFO threshold is hit. If CS or FStriggers the sampling, the data on SDI must be any one of the SELECT CHANNEL commands. This data is adummy code for setting the converter in the conversion state. It does not change the existing channel selectionset at the start of the operation until the FIFO is full. After the operation finishes, the host can read the FIFO,then reselect the channel and start the next REPEAT operation again; or immediately reselect the channel andstart the next REPEAT operation (by issuing CS, FS, or CSTAR), or reconfigure the converter and then starta new operation according to the new setting. If CSTART triggers the sampling, the host can also immediatelystart the next REPEAT (on the current channel) after the FIFO is full. Besides, if FS initiates the operation andCSTART triggers the sampling and conversions, CS must not toggle during the conversion. This mode allowsthe host to set up the converter, continue monitoring a fixed input, and to get a set of samples as needed.20POST OFFICE BOX 655303 DALLAS, TEXAS 75265•TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSSLAS266C – OCTOBER 2000 – REVISED MAY 2003conversion mode (continued)Sweep Mode (Mode 10): During each operation, all of the channels listed in the sweep sequence (D[4:3] ofthe CFR register) are sampled and converted at one time according to the programmed sequence. The resultsare stored in the FIFO. When the FIFO threshold is reached, an interrupt (INT) is generated, and the operationends. If the FIFO threshold is reached before all of the listed channels are visited, the remaining channels areignored. This allows the host to change the sweep sequence length. The mode 10 operation starts with theWRITE CFR command to set the sweep sequence. The following triggers (CS, FS, or CSTART, depending onthe interface) start the samplings and conversions of the listed channels in sequence until the FIFO thresholdis hit. If CS or FS starts the sampling, the SDI data must be any one of the SELECT commands to set theconverter in the conversion state. However, this command is a dummy code. It does not change the existingconversion sequence. After the FIFO is full, the converter waits for the FIFO READ. It does nothing before theFIFO READ or the WRITE CFR command is issued. The host must read the FIFO completely or write the CFR.If CSTART triggers the samplings, the host must issue an extra SELECT/CONVERSION command (select anychannel) via CS or FS after the FIFO READ or WRITE CFR. This extra period is named the arm period and isused to set the converter into the conversion state, but does not affect the existing conversion sequence.Besides, if FS initiates the operation and CSTART triggers the sampling and conversions, CS must not toggleduring the conversion.Repeat Sweep Mode (Mode 11): This mode works in the same way as mode 10, except that it is not necessaryto read the FIFO before the next operation after the FIFO threshold is hit. The next SWEEP can repeatimmediately, but the contents in the FIFO are replaced by the new results. The host can read the FIFOcompletely, then issue the next SWEEP or repeat the SWEEP immediately (with the existing sweep sequence)by issuing sampling/conversion triggers (CS, FS or CSTART) or change the device setting with the WRITE CFR.The memory effect of charge redistribution DAC exists when the mux switches from one channel to another.This degrades the channel-to-channel isolation if the channel changes after each conversion. For example, inmode 10 and 11, the isolation is about 70 dB for the sweep sequence 0-1-2-3-4 (refer to Figure 8). The memoryeffect can be reduced by increasing the sampling time or using the sweep sequence 0-0-2-2-4-4-6-6 andignoring the first sample of each channel. Figure 8 shows the typical isolation vs throughput rate when applyinga sine signal (35 kHz, 3.5 Vp-p) on CH0 and dc on CH1 converting both channels alternately and measuring theattenuation of the sine wave in CH1.CHANNEL-TO-CHANNEL ISOLATIONvsTHROUGHPUT100Channel-to-Channel Isoltaion – dB90807060050100Throughput – KSPS150200Figure 8POST OFFICE BOX 655303 DALLAS, TEXAS 75265•21SLAS266C – OCTOBER 2000 – REVISED MAY 2003TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSoperation cycle timingCS InitiatesOperation4 SCLKs12 SCLKs for Short44 SCLKs for Long18 OSC for Internal OSC†72 SCLK for External Clock15 nst(setup)†t(sample)12-bit CFR Data (Optional)t(convert)t(overhead)SDI4-bit CommandSDO14-bit Data (Previous Conversion)2-bit Don’t CareActive CS (FS Is Tied to High)CSTAR (For Extended Sampling) occurs ator after the rising edge of eleventh SCLKt–CSL to FSL4 SCLKs12 SCLKs for Short44 SCLKs for Long18 OSC for Internal OSC72 SCLK for External Clock15 nSt(delay)†t(setup)†4-bit Commandt(sample)12-bit CFR Data (Optional)t(convert)t(overhead)SDIFS InitiatesOperationSDO14-bit Data (Previous Conversion)2-bit Don’t CareActive CS (CS Can Be Tied to Low)Active FS†Non JEDEC terms used.CSTAR (For Extended Sampling) occurs ator after the rising edge of eleventh SCLKAfter the operation is finished, the host has several choices. Table 3 summarizes operation options.22POST OFFICE BOX 655303 DALLAS, TEXAS 75265•TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSSLAS266C – OCTOBER 2000 – REVISED MAY 2003operation cycle timing (continued)Table 3. Operation OptionsMODE00CONVERSION IS INITIATED BYCS1.Issue new Select/Read operation toread data and start new conversion.2.Reconfigure the device.FS1.Issue new Select/Read operation toread data and start new conversion.2.Reconfigure the device.CSTART1.Issue new CSTART to start nextconversion; old data lost.2.Issue new Select/Read operation toread data—Issue new CSTART tostart new conversion.3.Reconfigure the device.1.Read FIFO—Select channel—Startnew conversion. Channel must beselected after FIFO READ.2.Start new conversion (old data lost)with existing setting.3.Configure device again.1.Read FIFO—Arm Period—Start newconversion with existing setting2.Configure device—Arm Period—Newconversion (old data lost)1.Read FIFO—Arm Period—Start newConversion with existing setting2.Start new conversion with existingsetting. (old data lost)3.Configure device—Arm Period—Newconversion with new setting.011.Read FIFO—Select Channel—Startnew conversion. Channel must beselected after FIFO READ.2.Select Channel—Start newconversion (old data lost)3.Configure device again.1.Read FIFO—Start new conversionwith existing setting.2.Configure device—New conversion(old data lost)1.Read FIFO—Start new conversionwith existing setting.2.Start new conversion with the existingsetting.3.Configure device—Start newconversion with new setting.1.Read FIFO—Select Channel—Startnew conversion. Channel must beselected after FIFO READ.2.Select Channel—Start newconversion (old data lost)3.Configure device again.1.Read FIFO—Start new conversionwith existing setting.2.Configure device—New conversion(old data lost)1.Read FIFO—Start new conversionwith existing setting2.Start new conversion with the existingsetting.3.Configure Device—Start newconversion with new setting.1011operation timing diagramsThe FIFO read and write CFR are nonconversion operations. The conversion operation performs one of fourtypes of conversion: mode 00, 01, 10, and 11Write Cycle (WRITE CFR Command): Write cycle does not generate EOC or INT, nor does it carry out anyconversion.123456712131415161CSFSSDIORINTEOCSDONote:Signal May Not Exist. Don’t CareHi-ZID151D14ID131D12ID11ID10ID9ID4ID3ID2ID1ID0ID15Figure 9. Write Cycle, FS Initiates OperationPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•23SLAS266C – OCTOBER 2000 – REVISED MAY 2003TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSoperation timing diagrams (continued)123456712131415161CSFS = HighSDIINTOREOCSDOID151D14ID131D12ID11ID10ID9ID4ID3ID2ID1ID0ID15ID14Hi-ZNote:Signal May Not Exist. Don’t CareFigure 10. Write Cycle, CS Initiates Operation, FS = 1FIFO Read Operation: When the FIFO is used, the first command after INT is generated is assumed to be theFIFO read. The first FIFO content is sent out immediately before the command is decoded. If this command isnot a FIFO read, the output is terminated. Using more layers of the FIFO reduces the time taken to read multipleconversion results, because the read cycle does not generate an EOC or INT, nor does it make a dataconversion. Once the FIFO is read, the entire contents in the FIFO must be read out. Otherwise, the remainingdata is lost.1234SCLKCSFS = HighSDIINTOR56712131415161ID151D14ID131D12ID15ID14EOCSDOOD15OD14OD13OD12OD11OD10OD9OD4OD3OD2Hi-ZOD15OD14Notes:Signal May Not Exist.OD[15:2] is FIFO Contents. Don’t CareFigure 11. FIFO Read Cycle, CS Initiates Operation, FS = 124POST OFFICE BOX 655303 DALLAS, TEXAS 75265•TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSSLAS266C – OCTOBER 2000 – REVISED MAY 2003conversion operation48 SCLKs for Long Sampling16 SCLKs for Short Sampling123456712131415161CSFS in HighSDIINTt(SAMPLE)t(conv)Select ChannelID15ID14ID131D12ID15EOCORPrevious Conversion ResultOD15OD14OD13OD12OD11OD10OD9OD4OD3OD2SDO Hi-ZSDO goes to Hi-Z After 16th SCLKOD15The dotted line means signal may or may not exist.OD[15:2] is the result of previous conversion. Don’t CareFigure 12. Mode 00, CS Initiates Operation48 SCLKs for Long Sampling16 SCLKs for Short Sampling123456712131415161SCLKCSFSSelect ChannelSDIINTORID151D14ID131D12ID15t(SAMPLE)t(conv)EOCPrevious Conversion ResultSDO Goes Through Hi-Z After 16 SCLKOD4OD3OD2SDOOD15OD14OD13OD12OD11OD10OD9Hi-ZOD15The dotted line means signal may or may not exist.OD[15:2] is the result of previous conversion. Don’t CareFigure 13. Mode 00, FS Initiates OperationPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•25SLAS266C – OCTOBER 2000 – REVISED MAY 2003TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSconversion operation (continued)Select Channel16 SCLKCS Tied to LowCSTARTFSSDIINT*****PossibleSignalt(sample)Select Channel16 SCLKt(convert)**EOCORSDOPrevious Conversion ResultHi-ZPossible SignalData LostHi-ZConversion ResultHi-Z** Select Channel Don’t CareFigure 14. Mode 00, CSTART Triggers Sampling/Conversion, FS Initiates SelectCSFSSelect CH1Select AnyChannel** Hi-Z1/4 FIFO FULL**Select CH2**Select AnyChannel****SDISDOINT*****DATA1 of CH1DATA2 of CH1DATA1 of CH2DATA2 of CH21/4 FIFO FULLDon’t CarePossible Signal*** –– WRITE CFR** –– Select Channel* –– FIFO ReadMODE 01, FS Activates Conversion, FIFO Threshold = 1/4 FullRead FIFO After Threshold Is HitFigure 15. Mode 01, FS Initiates OperationsCSFSCSTARTSelect CH1Select CH2* Hi-Z*****SDI*****DATA1 of CH1DATA2 of CH1DATA1 of CH2DATA2 of CH21/4 FIFO FULLSDOINTDon’t CarePossible Signal*** –– WRITE CFR** –– Select Channel* –– FIFO Read1/4 FIFO FULLMODE 01, FS Initiates Select Period, CSTART Activates Conversion, FIFO Threshold = 1/4 Full,Read FIFO After Threshold Is HitFigure 16. Mode 01, CSTART Triggers Samplings/Conversions26POST OFFICE BOX 655303 DALLAS, TEXAS 75265•TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSSLAS266C – OCTOBER 2000 – REVISED MAY 2003conversion operation (continued)ConfigureConversionFrom CH0ConversionFrom CH3ConversionFrom CH0ConversionFrom CH3CSFSSDIINTSDO************************Hi-Z1st SweepDon’t CareCH0CH1CH2CH32nd SweepUsing ExistingConfigurationCH0*** Command = Configure Write for Mode 10, FIFO Threshold = 1/2 Full, Sweep Sequence: 0–1–2–3** COMMAND = Select Any Channel* COMMAND = Read FIFO1st FIFO ReadRead FIFO After FIFO Threshold Is Hit2nd FIFO ReadFigure 17. Mode 10, FS Initiates OperationsCS Tiedto LowFSCSTARTSDIINTSDODon’t Care*** Command = Configure Write for Mode 10, FIFO Threshold = 1/2 Full, Sweep Sequence: 0–0–2–2** COMMAND = Select Any Channel* COMMAND = Read FIFOHi-Z1st SweepCH0CH0CH2CH2CH0ConfigureConversionFrom CH0ConversionFrom CH2ConversionFrom CH0ConversionFrom CH2************2nd SweepUsing ExistingConfiguration1st FIFO ReadRead FIFO After FIFO Threshold Is Hit, FS Initiates Select Period2nd FIFO ReadFigure 18. Mode 10, CSTART Initiates OperationsConfigureConversionFrom CH0ConversionFrom CH3ConversionFrom CH0ConversionFrom CH3ConversionFrom CH0CSFS=HighSDIINTSDOSTART 2nd Round SWEEP CONVERSION,the DATA of the 1st Round Are Lost*************************CH0CH1CH2CH3Don’t CareREAD the DATA of 2ndSweep From FIFO*** Command = Configure Write for Mode 11, FIFO Threshold = 1/2 Full, Sweep Sequence: 0–1–2–3START 2nd Sweep conversion immediately (NO FIFO READ) after the 1st SWEEP completed.** COMMAND = Select Any Channel* COMMAND = Read FIFOFigure 19. Mode 11, CS Initiates OperationsPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•27SLAS266C – OCTOBER 2000 – REVISED MAY 2003TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSconversion operation (continued)ConfigureConversionFrom CH0ConversionFrom CH2ConversionFrom CH0ConversionFrom CH2CSFSCSTARTSDIINTSDO************1st SWEEPCH0CH0CH2CH2REPEATCH01st FIFO ReadDon’t Care*** Command = Configure Write for Mode 11, FIFO Threshold = 1/2 Full, Sweep Sequence: 0–0–2–2** COMMAND = Select Any Channel* COMMAND = Read FIFOPossible SignalRead FIFO After 1st SWEEP Completed2nd FIFO ReadFigure 20. Mode 11, CSTART Triggers Samplings/Conversionsconversion clock and conversion speedThe conversion clock source can be the internal OSC, or the external clock SCLK. When the external clock isused, the conversion clock is equal to SCLK/4. It takes 18 conversion clocks plus 15 ns to finish the conversion.If the external clock is selected, the conversion time (not including sampling time) is 18X(4/fSCLK)+15 ns. Table 4shows the maximum conversion rate (including sampling time) when the analog input source resistor is 1 kΩ.Table 4. Maximum Conversion RateDEVICESAMPLING MODE Short (16 SCLK)TLC3544/48(Rs = 1000)() Long (48 SCLK)Short (16 SCLK) Long (48 SCLK)CONVERSION CLKExternal SCLK/4External SCLK/4Internal 6.5 MHzInternal 6.5 MHzMAX SCLK(MHz)10251025CONVERSIONTIME (us)8.8154.8154.3854.705RATE (KSPS)113.4207.7228212.5FIFO operationSerial×8FIFOADC76543210SODFIFO FullFIFO 1/2 FullFIFO 3/4 FullFIFO 1/4 FullFIFO Threshold PointerFigure 21. FIFO Structure28POST OFFICE BOX 655303 DALLAS, TEXAS 75265•TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSSLAS266C – OCTOBER 2000 – REVISED MAY 2003FIFO operation (continued)The device has an 8-level FIFO that can be programmed for different thresholds. An interrupt is sent to the hostafter the preprogrammed threshold is reached. The FIFO is used to store conversion results in mode 01, 10,and 11, from either a fixed channel or a series of channels according to a preprogrammed sweep sequence.For example, an application may require eight measurements from channel 3. In this case, if the threshold isset to full, the FIFO is filled with 8 data conversions sequentially taken from channel 3. Another application mayrequire data from channel 0, 2, 4, and 6 in that order. The threshold is set to 1/2 full and sweep sequence isselected as 0–2–4–6–0–2–4–6. An interrupt is sent to the host as soon as all four data conversions are in theFIFO. The FIFO is reset after a power on and a WRITE CFR operation. The contents of the FIFO are retainedduring autopower down and software power down.Powerdown: The device has two power-down modes.AutoPower-Down Mode: The device enters the autopower-down state at the end of a conversion.In autopower-down, the power consumption reduces to about 1.8 mA when an internal reference is selected.The built-in reference is still on to allow the device to resume quickly. The resumption is fast enough for usebetween cycles. An active CS, FS, or CSTART resumes the device from power-down state. The power currentis 20 µA when an external reference is programmed and SCLK stops.Software Power-Down Mode: Writing 8000h to the device puts the device into the software power-down state,and the entire chip (including the built-in reference) is powered down. The power current is reduced to about20 µA if SCLK stops. Deselect CS to save power once the device is in the software power-down mode. An activeCS, FS, or CSTART restores the device. There is no time delay when an external reference is selected.However, if an internal reference is used, it takes about 20 ms to warm up.The configuration register is not affected by any of the power-down modes but the sweep operation sequencemust be started over again. All FIFO contents are retained in both power-down modes.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•29SLAS266C – OCTOBER 2000 – REVISED MAY 2003TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSTYPICAL CHARACTERISTICSINTEGRAL NONLINEARITYvsDIGITAL OUTPUT CODEINL – Integral Nonlinearity – LSB1.0Internal Reference = 4 VAVDD = 5 V, TA = 25°C0.50.0–0.5–1.00200040006000800010000120001400016000Digital Output CodeFigure 22DIFFERENTIAL NONLINEARITYvsDIGITAL OUTPUT CODEDNL – Differential Nonlinearity – LSB1.0Internal Reference = 4 VAVDD = 5 V, TA = 25°C0.50.0–0.5–1.00200040006000800010000120001400016000Digital Output CodeFigure 2330POST OFFICE BOX 655303 DALLAS, TEXAS 75265•TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSSLAS266C – OCTOBER 2000 – REVISED MAY 2003TYPICAL CHARACTERISTICSINL AND DNLvsFREE-AIR TEMPERATURE1.0Internal Reference = 4 VAVDD = 5 VZero Offset and Gain Error – LSB420–2–4–6–8Gain Error (LSB)–10–12–140.4–65–35–5255585–16–65External Reference = 4 VAVDD = 5 V–35–52555TA – Free-Air Temperature – °C85Zero Offset (LSB)ZERO OFFSET AND GAIN ERROR (LSB)vsFREE-AIR TEMPERATURE0.9INL and DNL – LSB0.8INL (LSB)0.70.6DNL (LSB)0.5TA – Free-Air Temperature – °CFigure 24FFT OF SNRvsFREQUENCY20–20FFT of SNR – dB–60–100–140–18001020304050607080Figure 25External Reference = 4 VAVDD = 5 VTA = 25°C200 KSPSInput Signal: 20 kHz, 0 dB90100f – Frequency – kHzFigure 26POST OFFICE BOX 655303 DALLAS, TEXAS 75265•31SLAS266C – OCTOBER 2000 – REVISED MAY 2003TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSTYPICAL CHARACTERISTICSSINADvsINPUT SIGNAL FREQUENCY90External Reference = 4 VAVDD = 5 VTA = 25°C8513.514.0ENOBvsINPUT SIGNAL FREQUENCYExternal Reference = 4 VAVDD = 5 VTA = 25°C80ENOB – Bits02000020k4000040k6000060k8000080k100000100kSINAD – dB13.07512.570f – Input Signal Frequency – Hz12.002000020k4000040k6000060k8000080k100000100kf – Input Signal Frequency – HzFigure 27THDvsINPUT SIGNAL FREQUENCY–80External Reference = 4 VAVDD = 5 VTA = 25°C–85105Figure 28SFDRvsINPUT SIGNAL FREQUENCYExternal Reference = 4 VAVDD = 5 VTA = 25°C100THD – dB–90SFDR – dB11020304050607080909895–9590–1008502000020k4000040k6000060k8000080k100000100kf – Input Signal Frequency – Hzf – Input Signal Frequency – kHzFigure 29Figure 3032POST OFFICE BOX 655303 DALLAS, TEXAS 75265•TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSSLAS266C – OCTOBER 2000 – REVISED MAY 2003TYPICAL CHARACTERISTICSSUPPLY CURRENT ATSOFTWARE POWER-DOWNvsFREE-AIR TEMPERATUREICC – Supply Current at Software Power Down– µA30Internal Reference = 4 VAVDD = 5 VSCLK = OFFAll Digital Input = DGNDor DVDDSUPPLY CURRENTvsFREE-AIR TEMPERATURE4.5External Reference = 4 VAVDD = 5 VCS = DGNDInternal OSC4.4ICC – Supply Current – mA254.3204.2154.1104.053.9–65–35–52555850–65–35–5255585TA – Free-Air Temperature – °CTA – Free-Air Temperature – °CFigure 31SUPPLY CURRENT ATAUTOPOWER-DOWNvsFREE-AIR TEMPERATURE4.0ICC – Supply Current at Autopower-Down – µAExternal Reference = 4 VAVDD = 5 VSCLK = OFFAll Digital Input = DGNDor DVDDFigure 323.53.02.52.01.5–65–35–5255585TA – Free-Air Temperature – °CFigure 33POST OFFICE BOX 655303 DALLAS, TEXAS 75265•33SLAS266C – OCTOBER 2000 – REVISED MAY 2003TLC3544, TLC35485-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIALANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTSAPPLICATION INFORMATIONinterface with hostFigure 34 shows examples of the interface between a single converter and a host DSP (TMS320C54xDSP)or microprocessor. The C54x is set as FWID = 1 (active pulse width = 1CLK), (R/X) DATDLY = 1 (1 bit data delay),CLK(X/R)P = 0 (transmit data are clocked out at rising edge of CLK, receive data are sampled on falling edgeof CLK), and FS(X/R)P = 1 (FS is active high). If multiple converters connect to the same C54x, use CS as thechip select.The host microprocessor is set as the SPI master with CPOL = 0 (active high clock), and CPHA = 1 (transmitdata is clock out at rising edge of CLK, receive data are sampled at falling edge of CLK). 16 bits (or more) pertransfer is required.VDDVDD10 kΩTMS320C54XFSRFSXDXDRCLKRCLKXIRQSCLKINT/EOCConverterCSFSSDISDOAinMOSIMISOSCKIRQHostMicroprocessorSS10 kΩ10 kΩConverterCSFSSDISDOSCLKINT/EOCAinSingle Converter Connects to DSPConverter Connects to MicroprocessorFigure 34. Typical Interface to Host DSP and Microprocessorsampling time analysisFigure 35 shows the equivalent analog input circuit of the converter. During the sampling, the input capacitor,Ci, has to be charged to VC, (VC = Vs ± voltage of 1/4 LSB = Vs ± [Vs/65532] for 14 bit converter).t(s) = Rt × Ci × In (65532) where Rt = Rs+ri, t(s) = Sampling timeDriving SourceVSRSVIData ConverterriVCVI = Input Voltage at AINVS = External Driving Source VoltageRS = Source Resistanceri = Equivalent Resistor of Mux., 1.5 kΩCI = Input Capacitance, 30 pF Max.VC = Capacitance Charging VoltageCIFigure 35. Equivalent Input Circuit Including the Driving SourceTMS320C54x is a trademark of Texas Instruments.34POST OFFICE BOX 655303 DALLAS, TEXAS 75265•PACKAGEOPTIONADDENDUM
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28-Aug-2008
PACKAGINGINFORMATION
OrderableDeviceTLC3544CDWTLC3544CDWG4TLC3544CPWTLC3544CPWG4TLC3544CPWRTLC3544CPWRG4TLC3544IDWTLC3544IDWG4TLC3544IPWTLC3544IPWG4TLC3548CDWTLC3548CDWG4TLC3548CDWRTLC3548CDWRG4TLC3548CPWTLC3548CPWG4TLC3548CPWRTLC3548CPWRG4TLC3548IDWTLC3548IDWG4TLC3548IDWRTLC3548IDWRG4TLC3548IPWTLC3548IPWG4TLC3548IPWR
Status(1)ACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVE
PackageTypeSOICSOICTSSOPTSSOPTSSOPTSSOPSOICSOICTSSOPTSSOPSOICSOICSOICSOICTSSOPTSSOPTSSOPTSSOPSOICSOICSOICSOICTSSOPTSSOPTSSOP
PackageDrawingDWDWPWPWPWPWDWDWPWPWDWDWDWDWPWPWPWPWDWDWDWDWPWPWPW
PinsPackageEcoPlan(2)
Qty20202020202020202020242424242424242424242424242424
25257070
Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)
Lead/BallFinishCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAU
MSLPeakTemp(3)Level-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEARLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEAR
2000Green(RoHS&
noSb/Br)2000Green(RoHS&
noSb/Br)252570702525
Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)
2000Green(RoHS&
noSb/Br)2000Green(RoHS&
noSb/Br)6060
Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)
2000Green(RoHS&
noSb/Br)2000Green(RoHS&
noSb/Br)2525
Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)
2000Green(RoHS&
noSb/Br)2000Green(RoHS&
noSb/Br)6060
Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)
2000Green(RoHS&
noSb/Br)
Addendum-Page1
PACKAGEOPTIONADDENDUM
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28-Aug-2008
OrderableDeviceTLC3548IPWRG4
(1)
Status(1)ACTIVE
PackageTypeTSSOP
PackageDrawingPW
PinsPackageEcoPlan(2)
Qty24
2000Green(RoHS&
noSb/Br)
Lead/BallFinishCUNIPDAU
MSLPeakTemp(3)Level-2-260C-1YEAR
Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)
EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms\"Lead-Free\"or\"Pb-Free\"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.
Green(RoHS&noSb/Br):TIdefines\"Green\"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)
(3)
MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
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PACKAGEMATERIALSINFORMATION
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9-Apr-2009
TAPEANDREELINFORMATION
*Alldimensionsarenominal
Device
PackagePackagePinsTypeDrawingTSSOPTSSOPTSSOP
PWPWPW
202424
SPQ
ReelReelDiameterWidth(mm)W1(mm)330.0330.0330.0
16.416.416.4
A0(mm)B0(mm)K0(mm)
P1(mm)8.08.08.0
WPin1(mm)Quadrant16.016.016.0
Q1Q1Q1
TLC3544CPWRTLC3548CPWRTLC3548IPWR
200020002000
6.956.956.95
7.18.38.3
1.61.61.6
PackMaterials-Page1
PACKAGEMATERIALSINFORMATION
www.ti.com
9-Apr-2009
*Alldimensionsarenominal
DeviceTLC3544CPWRTLC3548CPWRTLC3548IPWR
PackageType
TSSOPTSSOPTSSOP
PackageDrawing
PWPWPW
Pins202424
SPQ200020002000
Length(mm)
346.0346.0346.0
Width(mm)346.0346.0346.0
Height(mm)
33.033.033.0
PackMaterials-Page2
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 MECHANICAL DATA PW (R-PDSO-G**) 14 PINS SHOWNPLASTIC SMALL-OUTLINE PACKAGE0,651480,300,190,10M0,15 NOM4,504,306,606,20Gage Plane0,251A70°–8°0,750,50Seating Plane1,20 MAX0,150,050,10PINS **DIMA MAX83,10145,10165,10206,60247,90289,80A MIN2,904,904,906,407,709,604040064/F 01/97NOTES:A.B.C.D.All linear dimensions are in millimeters.This drawing is subject to change without notice.Body dimensions do not include mold flash or protrusion not to exceed 0,15.Falls within JEDEC MO-153POST OFFICE BOX 655303 DALLAS, TEXAS 75265•IMPORTANTNOTICE
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FollowingareURLswhereyoucanobtaininformationonotherTexasInstrumentsproductsandapplicationsolutions:ProductsAmplifiers
DataConvertersDLP®ProductsDSP
ClocksandTimersInterfaceLogic
PowerMgmtMicrocontrollersRFID
RF/IFandZigBee®Solutions
amplifier.ti.comdataconverter.ti.comwww.dlp.comdsp.ti.comwww.ti.com/clocksinterface.ti.comlogic.ti.compower.ti.commicrocontroller.ti.comwww.ti-rfid.comwww.ti.com/lprfApplicationsAudio
AutomotiveBroadbandDigitalControlMedicalMilitary
OpticalNetworkingSecurityTelephony
Video&ImagingWireless
www.ti.com/audiowww.ti.com/automotivewww.ti.com/broadbandwww.ti.com/digitalcontrolwww.ti.com/medicalwww.ti.com/militarywww.ti.com/opticalnetworkwww.ti.com/securitywww.ti.com/telephonywww.ti.com/videowww.ti.com/wirelessMailingAddress:TexasInstruments,PostOfficeBox655303,Dallas,Texas75265
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