Volatile Memories
1. Introduction
Memories often account for the majority of transistor in a CMOS system and may be divided into categories as shown in Figure 1.1. Basically, two classes can be roughly seen:volatile memories and non-volatile memories. Volatile memory retains its data as long as power is applied, while nonvolatile memory will hold data indefinitely.
The memory cells used in volatile memories can further be divided into static structures and dynamic structures. Static cells use some form of feedback to maintain their state, while dynamic cells use charge stored on a floating capacitor through an access transistor is off, so dynamic cells must be periodically read and rewritten to refresh their state. Static random access memories (SRAMs) are faster and less troublesome, but require more area per bit than their dynamic counterparts (DRAMs).
We begin this report with SRAM, the most widely used form of on-chip memory. Next, we analyze the DRAM cells and their properties as what we do about SRAM. And at the end of the report, we will discuss the application areas of these memories, and will list some of the important parameters.
Figure 1.1 Major Class of CMOS Memories
2. Static Random Access Memory (SRAM)
2.1 The Bistability Principle
Static memories use positive feedback to create a bistable circuit — a circuit having two stable states that represent 0 and 1. The basic idea is shown in Figure 2.1a, which shows two inverters connected in cascade along with a voltage-transfer characteristic typical of such a circuit. The resulting circuit has only three possible operation points (A,B and C), as demonstrated on the combined VTC. It is easy to prove the validity of the following important conjecture:
When the gain of the inverter in the transient region is larger than 1, A and B are the only stable operation points, and C is a metastable operation point.
The two stable operation points can represent 0 and 1 in a digital circuit, such as in static memories.
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Figure 2.1 Two cascaded inverters (a) and their VTCs(b)
2.2 SRAM cell
The fundamental building block of a static RAM is SRAM cell which is introduced in Figure 2.2. The bistable circuit is employed in this 6-T SRAM cell, so the storage of SRAM is based on positive feedback which we have discussed before. The cell is activated by raising the word line and is read or written through the bit line.
Figure 2.2 six-transistor CMOS SRAM cell
2.2.1 Operation of SRAM cell
To understand the operation of the memory cell, let us consider the read and write operations in sequence. While doing so, we also derive the transistor-sizing constraints. (a) CMOS SRAM Read Operation
Assume that a 1 is stored at Q. We further assume that both bit lines are pre-charged to 2.5V before the read operation is initiated. The read cycle is started by asserting the word line, enabling both pass transistorsM5andM6after the initial word line delay. During a correct read operation, the values stored in Q and Qare transferred to the bit lines by leaving BL at its pre-charged value and by dischargingBLthroughM1~M5. This is illustrated in Figure 2.2.
Consider theBLside of the cell. The bit line capacitance for larger memories is in the pF range. Consequently, the value ofBLstays at the pre-charged valueVDDupon enabling of
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V
the read operation (WL→1). This series combination of the two NMOS transistors pulls downBLtowards ground. As the difference between BL andBLbuilds up, the sense amplifier is activated to accelerate the reading process.
The boundary constrains on the device sizes can be derived by solving the current equation at the maximum allowed value of the voltage rippleV. We ignore the body effect for simplicity and write:
Figure 2.2 Simplified model of CMOS SRAM cell during read operationID5ID1KnnCoxWLV2]Kn,M1[(VDDVTn)V]222VDS5Kn,M5[(VDDVVTn)VDS5V22VDS5CR(VDDVTn)VDS(1CR)CR(VDDVTn)5CRW1L1L5W5CR
The value of the voltage riseVas a function of CR for 0.25mtechnology is plotted in Figure 2.3. To keep the node voltage from rising above the transistor threshold (about
0.4V), the cell ratio must be greater than 1.2. For large memory arrays, it is desirable to keep the cell size minimal while maintaining read stability.
Now, let us discuss the reason why CR should be larger than 1.2.If CR<1.2, then
Figure 2.3 Voltage rise inside the cell upon read versus cell ratio
V >0.4, then, M3 will be on and the value of Q will be pulled down to zero
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through it; However, Q should be 1. This type of malfunction is frequently called a read upset. As illustrated in Figure 2.4. To avoid this malfunction, a careful sizing of the transistors is necessary.A preferred solution is to minimize the size of the pass transistor, and increase the width of the NMOS pull-down M5 to meet the stability constraint.
VFigure 2.4 Read upset malfunction
(b) COMS SRAM Write Operation
We assume that a 1 is stored in the cell (Q=1). A 0 is written in the cell by setting BLto 1 and BL to 0. During the initiation of a write, the schematic of the SRAM cell can be simplified to the model of Figure 2.5. It is reasonable to assume that the gates of transistors M1andM4stay atVDDand GND, respectively, as long as the switching has not commenced.
Figure 2.5 Simplified model of CMOS SRAM cell during write operationFigure 2.6 A contradiction in CMOS SRAM cell during write operation
Note thatQside of the cell cannot be pulled high enough to ensure the writing of 1. The sizing constraint, imposed by the read stability, ensures that this voltage is kept below 0.4V. Therefore, the new value of the cell has to be written through transistorM6. However, a contradiction phenomenon will appear if the value of Q is not pull down to 0 quickly which is shown in Figure 2.6. At the beginning of this write operation (write 0 into the cell), the voltage of Q (1 is stored) is bigger than 0.4V, thenM1is on and pulls the value of Q down to ground. So we must make sure that the voltage of Q should be pulled down quickly throughM4andM6, with the value of BL is 0.
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A reliable writing of the cell is ensured if we can pull node Q low enough—this is, below the threshold value of the transistorM1. The condition for this to occur can be derived by writing out the dc current equations at the desired threshold point, as follows:
ID4ID6kn,M6[(VDDVTn)VQ2VQ22]kp,M4[(VDD|VTp|)VDS4442VDS42]2VDSpVQVDDVTn(VDDVTn)2PR[(VDD|VTp|)VDS]n2W4PRW6L4L4
The dependence of VQon PR for a 0.25mprocess is plotted in Figure 2.7. The lower PR, the lower the value of VQ. If we wish to pull the node belowVTn, the pull-up ratio has to be below 1.8.
Figure 2.7 Voltage written into the cell versus pull-up ratio
2.3 Summary
When analyzing the transient behavior of the SRAM cell, one realizes that the read operation is the critical one. It requires the (dis)charging of the large bit line capacitance through the stack of the small transistors of the selected cell. However, the write time is dominated by the propagation delay of the cross-couple inverter pair, as the drivers that force BL andBLto desired values can be large. To accelerate the read time, SRAMs use sense amplifier is activated, and it quickly discharges one of the bit lines.
3. Dynamic Random Access Memory (DRAM)
3.1 Three Transistor Dynamic Memory Cell
The 3T architecture DRAM cell is shown in Figure 3.1. This cell formed the core of the first popular MOS semiconductor memories such as the first 1-Kbit memory from Intel. While replaced by more area efficient cells in the very large memories of today, it is still
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the cell of choice in many memories embedded in application specific integrated circuits. This can be attributed to its relative simplicity in both design and operation.
(a)(b)Figure 3.1 Three-transistor DRAM cell
(a) 3T DRAM cell write/read operation
The cell is written to by placing the appropriate data value on BL1 and asserting
the write-word line (WWL).
The data is retained as charge on capacitance CS once WWL is lowered. When reading the cell, the read-word line (RWL) is raised. The storage transistor
M2 is either on or off depending upon the stored value.
The bit line BL2is either clamped to VDD with the aid of a load device or is
pre-charged to either VDD or VDDVT;
The series connection of M2 and M3pulls BL2 low when a ‘1’ is stored. And
BL2 remains high in the opposite case. The process is plotted in Figure 3.2.
Writing operationReading operation(a)Figure 3.2 3Tcell Reading/Writing operation and the signal waveforms during read and write(b)(b)Properties of 3T DRAM cell
In contrast to the SRAM cell, no constraints exist on the device ratios. This is a
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common property of dynamic circuits. The choice of device sizes is solely based on performance and reliability considerations;
In contrast to other DRAM cells, reading the 3T cell contents is nondestructive; No special process steps are needed. The storage capacitance is nothing more
than the gate capacitance of the readout device, and this makes the 3T cell attractive for embedded memory applications; The value stored on the storage node X when writing a ’1’ equals VWWL-VThn.
This threshold loss reduces the current flowing throughM2during a read operation and increases the read access time. To prevent this, some designs bootstrap the word-line voltage, or in other words, raise VWWL to a value higher than VDD;
3.2 One Transistor Dynamic Memory Cell
Another structure called on-transistor DRAM cell can be obtained by reducing two transistors and sacrifice in some of the cell properties. The 1T DRAM cell is undoubtedly the most pervasive dynamic DRAM cell in commercial memory design. A schematic is shown in Figure 3.2.
(a)(b)Figrue3.3 One-transistor DRAM cell
(a) Write Operation
During a write cycle, the data value is placed on the bit line BL, and the word line
WL is raised. Depending on the data value, the cell capacitance is either charged or discharged.
There is no any questions during in writing one ‘0’ into a cell, however, writing
a ‘1’ into the cell may need more time to discuss;
We can see that the voltage at the node X is : VxVWLVthn Observe that a threshold voltage is lost, which reduces the available charge.
However, this charge loss can be circumvented by bootstrapping the word lines to
a value higher than VDD; And in this report, when restored a ‘1’ in the cell, we assume that the voltage at node X is V X V DD V thn with V WL DD . V
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(b) Read Operation
Before a read operation is performed, the bit line is pre-charged to a voltage VPRE. Upon asserting the word line, charge redistribution takes place between the bit
line and storage capacitance.
This results in a voltage change on the bit line, the direction of which determines
the value of the data stored.
According to the charge-sharing equation, the voltage swing on the bit line during
reading operation can be computed as follows:
VXCSVPRECBLVBL(CBLCS)VVBLVPREV(VXVBL)V(VXVPRE)CSCSCBLCSCC(VXVPRE)SVSCBLCBLCBL
Where CBL is the bit line capacitance, VBL the potential of the bit line after the
charge redistribution, and Vx the initial voltage over the cell capacitance Cs; The ratio C S ( S BL C C)is called the charge-transfer ratio and ranges between
1% and 10%;
The read and write operation of 1T cell and corresponding signal waveforms during write and read is shown in Figure 3.4.
X(a)(b)(c)Properties of 1T DRAM cell
A 1T DRAM requires the presence of a sense amplifier for each bit line to be
functional; This is a result of the charge-redistribution-based readout;
The readout of the 1T DRAM cell is destructive. This means that the amount of
charge stored in the cell is modified during the read operation. After a successful read operation, the original value must be restored. Read and refresh operations are therefore intrinsically intertwined in a 1T DRAM. Typically, the output of the sense amplifier is imposed onto the bit line during the readout. Keeping WL high ensures that the cell charge is restored during that period. This is illustrated in Figure 3.5.
Unlike the 3T cell that relies on charge storage on a gate capacitance, the 1T cell
requires the presence of an extra capacitance that must be explicitly included in
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Figure 3.4 1T cell Reading/Writing operation and the signal waveforms during read and write
the design; For reliability, the charge-transfer should keep large;
VBLV(1)VPREDV(1)V(0)Sense amp activatedtWord line activatedFigure 3.5 Bit line voltage waveform during read operation (for 1 to 0 data values)
Sense Amplifier function: Speed up the readout; Drive the bit lines to the full signal range after sensing for refreshing;
3.3 Summary
We can see that the basic operational concepts are extremely simple. DRAMs store their contents as charge on a capacity rather than in a feedback loop, and this is the essential difference with SRAMs. More information about the difference between SRAM and DRAM is listed in table 3.1. Table 3.1 The difference between SRAM and DRAM SRAM Data stored as long as supply is applied; Larger (6 transistors/cell); Fast; Differential (usually) (bit lines);
DRAM Periodic refresh required; Smaller (1 or 3 transistors/cell); Slower; Single ended (bit line); 4. Conclusion
Through we only discuss the class of volatile memories in this report, for a good understanding and a complete comparison, we list application area for the various memory types not only volatile memories. The numbers in table 4.1 are orders of magnitudes and may vary between different memory vendors. Table 4.1 provides an overview of some types of memories with respect to some important parameters that characterize them. The characteristic values of these parameters render each type of memory suitable for application areas. These areas are summarized in table 4.2. Table 4.1 Characteristics of different memory types DEVICE Components per cell Cell area Chip area Max. of programming/erasing cycles Programming time 10~100ns 30~100ns — 5~10s 1~10sper ∞ ∞ 1 104 SRAM 6 4~6 4~4.5 DRAM 1 or 3 1.5 1.5 ROM 1 1 1 EPROM 1 1.5 1.5 EEPROM 2.5 4 4 105 FLASH 1 1.5 1.5 10~1046 byte 5~10s 9
Access time No power Retention time supply Power supply 20~100ns 0 ∞ 30~100ns 0 10~100ns 20~150ns 5~150ns 20~150ns ∞ 2ms >10 years >10 years >10 years Table 4.2 Application areas for the various memory types Memory type SRAM Application areas Super-fast system, low-power system, cache memories in PCs, workstations, telecommunication, multimedia computers, networking applications, cell phones, supercomputers, mainframes, servers, embedded memories. Medium to high speed, large computer systems, low-cost systems, large volumes, DRAM PC, hard disk drives, graphics boards, printer applications, embedded memories, embedded logic. Large volumes, video games, character generators, laser printer fonts, dictionary ROM EPROM EEPROM data in word processors, sound source data in electronic musical instruments, embedded memories. CD-ROM drives, code storage, modems, embedded memories. Military applications, flight controllers, consumer applications, modems, cellular and cordless telephones, disk drives, printers, air bags braking systems, car radios, smart card, embedded memories. Portable systems, communication systems, code storage, memory PC cards, BIOS FLASH storage, digital cameras, palm tops, battery powered applications, digital cellular phones, embedded memories, MP3 players. 5. References
1. Sung-Mo Kang , Yusuf Leblebici
CMOS Digital Integrated Circuits: Analysis and Design Publishing House of Electronic Industry, China. 2. John P. Uyemura
Introduction to VLSI Circuits and Systems
Publishing House of Electronic Industry, China. 3. David A. Hodges, et al.
Analysis and Design of Digital Integrated Circuits: In deep submicron technology Publishing House of Electronic Industry, China. 4. Neil H.E Weste, et al.
CMOS VLSI Design: A Circuit and Systems Perspective
Addison-Wesley, New York. 5. Jan M. Rabaey, et al.
Digital Integrated Circuits: A Design Perspective Prentice Hall, New York.
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